AD73322–SPECIFICATIONS1 AD73322A Parameter Min Typ Max Units Test Conditions/Comments REFERE" />
參數(shù)資料
型號(hào)： AD73322LARUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 12/43頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR FRONTEND DL 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
通道數(shù)： 4
功率（瓦特）： 73mW
電壓 - 電源，模擬： 2.7 V ~ 5.5 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.5 V
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
–2–
REV. B
AD73322–SPECIFICATIONS1
AD73322A
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
REFERENCE
5VEN = 0
REFCAP
Absolute Voltage, VREFCAP
1.08
1.2
1.32
V
REFCAP TC
50
ppm/
°C 0.1 F Capacitor Required from
REFOUT
REFCAP to AGND2
Typical Output Impedance
130
Absolute Voltage, VREFOUT
1.08
1.2
1.32
V
Unloaded
Minimum Load Resistance
1
k
Maximum Load Capacitance
100
pF
INPUT AMPLIFIER
Offset
±1.0
mV
Maximum Output Swing
1.578
V
Max Output Swing = (1.578/1.2)
× VREFCAP
Feedback Resistance
50
fC = 32 kHz
Feedback Capacitance
100
pF
ANALOG GAIN TAP
Gain at Maximum Setting
+1
Gain at Minimum Setting
–1
Gain Resolution
5
Bits
Gain Step Size = 0.0625
Gain Accuracy
±1.0
%
Output Unloaded
Settling Time
1.0
s
Tap Gain Change of –FS to +FS
Delay
0.5
s
ADC SPECIFICATIONS
5VEN = 0
Maximum Input Range at VIN
2, 3
1.578
V p-p
Measured Differentially
–2.85
dBm
Max Input = (1.578/1.2)
× VREFCAP
Nominal Reference Level at VIN
1.0954
V p-p
Measured Differentially
(0 dBm0)
–6.02
dBm
Absolute Gain
PGA = 0 dB
–0.5
0.4
+1.2
dB
1.0 kHz, 0 dBm0
PGA = 38 dB
–1.5
–0.7
+0.1
dB
1.0 kHz, 0 dBm0
Gain Tracking Error
±0.1
dB
1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)
Refer to Figure 5
PGA = 0 dB
72
78
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
78
dB
300 Hz to 3400 Hz; fSAMP = 8 kHz
55
57
dB
0 Hz to fSAMP/2; fSAMP = 64 kHz
PGA = 38 dB
52
56
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
Total Harmonic Distortion
PGA = 0 dB
–84
–73
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 38 dB
–70
–60
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
Intermodulation Distortion
–65
dB
PGA = 0 dB
Idle Channel Noise
–71
dBm0
PGA = 0 dB
Crosstalk
ADC-to-DAC
–100
dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC-to-ADC
–100
dB
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
–70
dB
Input Amplifiers Included in Input Channel
DC Offset
–30
+10
+45
mV
PGA = 0 dB
Power Supply Rejection
–65
dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay4, 5
25
s
Input Resistance at PGA
2, 4, 6
20
k
Input Amplifiers Bypassed
DIGITAL GAIN TAP
Gain at Maximum Setting
+1
Gain at Minimum Setting
–1
Gain Resolution
16
Bits
Tested to 5 MSBs of Settings
Delay
25
s
Includes DAC Delay
Settling Time
100
s
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
(AVDD = +3 V
10%; DVDD = +3 V
10%; DGND = AGND = 0 V, fDMCLK =
16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
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AD73322LARZ 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
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