參數(shù)資料
型號(hào): AD7194BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 47/57頁
文件大?。?/td> 0K
描述: IC ADC 24BIT SPI 4.8K 32-LFCSP
產(chǎn)品培訓(xùn)模塊: Weigh Scale Introduction
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 4.8k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-WQ(5x5)
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)差分,單極;8 個(gè)差分,雙極;16 個(gè)偽差分,單極;16 偽差分,雙極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
其它名稱: AD7194BRUZ
AD7194BRUZ-ND
AD7194
Data Sheet
Rev. A | Page 50 of 56
FAST SETTLING MODE (CHOP ENABLED)
Chop can be enabled in the fast settling mode. With chop
enabled, the ADC offset and offset drift are minimized. The
analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins are then inverted, and another settled conversion
is obtained. Subsequent conversions are averaged so that the
offset is minimized. This continuous swapping of the analog
input pins and the averaging of subsequent conversions means
that the offset drift is also minimized.
Chopping does not change the output data rate. However, the
settling time equals
tSETTLE = 2/fADC
Consequently, if chop is enabled, the sinc4 filter is selected, FS[9:0]
is set to 6 and averaging by 16 is enabled, and the output data
rate is equal to 42.1 Hz. Therefore, the conversion time equals
1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms.
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