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| 型號(hào)： | AD7194BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SPI 4.8K 32-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Weigh Scale Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)差分，單極；8 個(gè)差分，雙極；16 個(gè)偽差分，單極；16 偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
| 其它名稱： | AD7194BRUZ AD7194BRUZ-ND |
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Data Sheet
AD7194
Rev. A | Page 23 of 56
Table 20. Operating Modes (MD)
MD2
MD1
MD0
Mode
0
Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs
conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register
go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the
communications register to 1, which enables continuous read. When continuous read is enabled, the conversions
are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the
ADC to output each conversion by writing to the communications register. After power-on, a reset, or a recon-
figuration of the ADC, the complete settling time of the filter is required to generate the first valid conversion.
Subsequent conversions are available at the selected output data rate, which is dependent on filter choice.
0
1
Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion on the selected channel. The internal clock requires 200 s typically to power up and settle. The ADC
then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed
in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data
register until another conversion is performed. RDY remains active (low) until the data is read or another conversion
is performed.
0
1
0
Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks
continue to be provided.
0
1
Power-down mode. In power-down mode, all AD7194 circuitry is powered down. The external crystal, if selected,
remains active.
1
0
Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1
0
1
Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is
placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register
of the selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed
to minimize the full-scale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the
internal full-scale calibration.
1
0
System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended
each time that the gain of a channel is changed.
1
System full-scale calibration. The user should connect the system full-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended
each time the gain of a channel is changed.
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| AD7194BCPZ-REEL | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7194BCPZ-REEL7 | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation |
| AD7195BCPZ | 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7195BCPZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 4.8KSPS CSP-32 |
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