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| 型號： | AD7148ACPZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 16LFCSP |
| 標準包裝： | 1 |
| 類型： | 電容性 |
| 觸摸面板接口： | 2 線 |
| 輸入數(shù)/鍵： | 8 鍵 |
| 分辨率（位）： | 16 b |
| 數(shù)據(jù)接口： | I²C，串行 |
| 數(shù)據(jù)速率/采樣率 (SPS，BPS)： | 250k |
| 電壓基準： | 內(nèi)部 |
| 電源電壓： | 2.6 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 其它名稱： | AD7148ACPZ-1500RL7DKR |
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AD7148
Rev. A | Page 13 of 56
CAPACITANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7148 has a Σ-Δ
architecture with 16-bit resolution. There are eight possible inputs
to the CDC that are connected to the input of the converter
through a switch matrix. The sampling frequency of the CDC
is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
the DECIMATION bits of the PWR_CONTROL register
(Address 0x000[9:8]), as listed in Table 8.
Table 8. CDC Decimation Rate
DECIMATION Bits
Decimation Rate
CDC Output Rate
per Stage (ms)
00
256
3.072
01
128
1.536
10
64
0.768
11
64
0.768
The decimation process on the AD7148 is an averaging process,
during which a number of samples are taken, and the averaged
result is output. Due to the architecture of the digital filter used,
the number of samples taken (per stage) is equal to 3× the decima-
tion rate. That is, 3 × 256 samples or 3 × 128 samples are averaged
to obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; thus, a trade-off is possible
between a noise-free signal and speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7148 to
null the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground. Best practice
is to ensure that the CDC output for any stage is approximately
equal to midscale (~32,700) when no sensor is active.
The simplified block diagram in Figure 20 shows how to apply
the STAGEx_OFFSET registers to null the offsets. The 6-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the
offset DAC to provide 0.32 pF resolution offset adjustment over a
range of 20 pF. Apply the positive and negative offsets to either the
positive or the negative CDC input using the NEG_AFE_OFFSET
and POS_AFE_OFFSET bits.
This process is required only once during the initial capacitance
sensor characterization.
0
71
55
-01
9
POS_AFE_OFFSET
16-BIT
CDC
NEG_AFE_OFFSET
+DAC
(20pF RANGE)
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
6
16
CIN
+
_
–DAC
(20pF RANGE)
CINx_CONNECTION_SETUP
BITS
Figure 20. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7148 has an on-chip sequencer to implement conversion
control for the input channels. Up to eight conversion stages
can be performed in one sequence. Each of the eight conversion
stages can measure the input from a different sensor. By using
the Bank 2 registers, each stage can be uniquely configured to
support multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE0 through
STAGE7, or a button sensor can be assigned to STAGE0. For each
conversion stage, the input mux that connects the CINx inputs to the
converter can have a unique setting.
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| AD7148ACPZ-1REEL | 功能描述:IC CAP-TO-DGTL CONV PROG 16LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 觸摸屏控制器 系列:- 標準包裝:96 系列:- 類型:- 觸摸面板接口:- 輸入數(shù)/鍵:- 分辨率（位）:- 評估套件:* 數(shù)據(jù)接口:- 數(shù)據(jù)速率/采樣率 (SPS，BPS):- 電壓基準:- 電源電壓:- 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD7150 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultra Low Power, 2 Channel, Capacitance Converter for Proximity Sensing |
| AD7150BRMZ | 功能描述:IC CAP CONV 2CH ULT LP 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD7150BRMZ-REEL | 功能描述:IC CAP CONV 2CH ULT LP 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD7151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultra-Low Power, 1-Channel, Capacitance Converter for Proximity Sensing |
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