I2C-COMPATIBLE SERIAL INTERFACE T" />
參數(shù)資料
型號(hào)： AD7148ACPZ-1500RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/57頁(yè)
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 16LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容性
觸摸面板接口： 2 線
輸入數(shù)/鍵： 8 鍵
分辨率（位）： 16 b
數(shù)據(jù)接口： I²C，串行
數(shù)據(jù)速率/采樣率 (SPS，BPS)： 250k
電壓基準(zhǔn)： 內(nèi)部
電源電壓： 2.6 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
其它名稱： AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 28 of 56
I2C-COMPATIBLE SERIAL INTERFACE
The AD7148 supports the industry standard 2-wire I2C serial inter-
face protocol. The two wires associated with the I2C timing are the
SCLK and the SDA inputs. The SDA is an I/O pin that allows both
register write and register readback operations. The AD7148 is
always a slave device on the I2C serial interface bus.
It has a single fixed 7-bit device address, Address 0101 110. The
AD7148 responds when the master device sends its device address
over the bus. The AD7148 cannot initiate data transfers on the bus.
Table 15. AD7148 I2C Device Address
DEV
A6
DEV
A5
DEV
A4
DEV
A3
DEV
A2
DEV
A1
DEV
A0
0
1
0
1
0
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line, SDA,
while the serial clock line, SCLK, remains high. This indicates
that an address/data stream follows.
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus now remain idle
while the selected device waits for data to be read from, or written
to it. If the R/W bit is a 0, the master writes to the slave device.
If the R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Transitions on the data line must occur during the low
period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
can be interpreted as a stop signal. The number of data bytes
transmitted over the serial bus in a single read or write operation
is limited only by what the master and slave devices can handle.
When all data bytes are read or written, a stop condition is estab-
lished. A stop condition is defined by a low-to-high transition
on SDA, while SCLK remains high. If the AD7148 encounters
a stop condition, it returns to its idle condition, and the address
pointer register resets to Address 0x00.
Writing Data over the I2C Bus
The process for writing to the AD7148 over the I2C bus is shown in
Figure 38 and Figure 40. The device address is sent over the bus
followed by the R/W bit set to 0. This is followed by two bytes of
data that contain the 10-bit address of the internal data register
to be written. The following bit map shows the upper register
address bytes. Note that Bit 7 to Bit 2 in the upper address byte
are don’t care bits. The address is contained in the 10 LSBs of
the register address bytes.
MSB
LSB
7
6
5
4
3
2
1
0
X
Register
Address
Bit 9
Register
Address
Bit 8
The following bit map shows the lower register address bytes.
MSB
LSB
7
6
5
4
3
2
1
0
Reg
Add
Reg
Add
Reg
Add
Reg
Add
Reg
Add
Reg
Add
Reg
Add
Reg
Add
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7148 address pointer register automatically increments
after each write, allowing the master to sequentially write to all
registers on the AD7148-1 in the same write transaction. However,
the address pointer register does not wrap around after the last
address.
Any data written to the AD7148 after the address pointer has
reached its maximum value is discarded.
All registers on the AD7148 have 16 bits. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even number
of data bytes.
To finish the transaction, the master generates a stop condition
on SDO or generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7148, the address pointer register must first
be set to the address of the required internal register. The master
performs a write transaction and writes to the AD7148 to set the
address pointer. The master then outputs a repeat start condition
to keep control of the bus or, if this is not possible, ends the write
transaction with a stop condition. A read transaction is initiated,
with the R/W bit set to 1.
The AD7148 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This operation is shown in
Because the address pointer automatically increases after each
read, the AD7148 continues to output readback data until the
master puts a no acknowledge and a stop condition on the bus.
If the address pointer reaches its maximum value, and the master
continues to read from the part, the AD7148 repeatedly sends
data from the last register addressed.
相關(guān)PDF資料
PDF描述
MS27467P9B98SA CONN PLUG 3POS STRAIGHT W/SCKT
VE-J1J-MX-F1 CONVERTER MOD DC/DC 36V 75W
MS27484T10B35PB CONN PLUG 13POS STRAIGHT W/PINS
SY100E416JI IC LINE RCVR QUINT DIFF 28-PLCC
MS27467T15F19PD CONN PLUG 19POS STRAIGHT W/PINS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7148ACPZ-1REEL 功能描述:IC CAP-TO-DGTL CONV PROG 16LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 觸摸屏控制器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 類型:- 觸摸面板接口:- 輸入數(shù)/鍵:- 分辨率（位）:- 評(píng)估套件:* 數(shù)據(jù)接口:- 數(shù)據(jù)速率/采樣率 (SPS，BPS):- 電壓基準(zhǔn):- 電源電壓:- 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD7150 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultra Low Power, 2 Channel, Capacitance Converter for Proximity Sensing
AD7150BRMZ 功能描述:IC CAP CONV 2CH ULT LP 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD7150BRMZ-REEL 功能描述:IC CAP CONV 2CH ULT LP 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD7151 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultra-Low Power, 1-Channel, Capacitance Converter for Proximity Sensing
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*