參數(shù)資料
型號(hào)： AD7148ACPZ-1500RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/57頁(yè)
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 16LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容性
觸摸面板接口： 2 線
輸入數(shù)/鍵： 8 鍵
分辨率（位）： 16 b
數(shù)據(jù)接口： I²C，串行
數(shù)據(jù)速率/采樣率 (SPS，BPS)： 250k
電壓基準(zhǔn)： 內(nèi)部
電源電壓： 2.6 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
其它名稱： AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 25 of 56
07
15
5-
0
34
Σ-Δ
16-BIT
CDC
16
STAGEx_MAX_WORD0
STAGEx_MAX_WORD1
STAGEx_MAX_WORD2
STAGEx_MAX_WORD3
STAGEx_MAX_AVG
BANK 3 REGISTERS
STAGEx_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGEx_MAX_TEMP
BANK 3 REGISTERS
STAGEx_MIN_WORD0
STAGEx_MIN_WORD1
STAGEx_MIN_WORD2
STAGEx_MIN_WORD3
STAGEx_MIN_AVG
BANK 3 REGISTER3
STAGEx_LOW_THRESHOLD
BANK 3 REGISTERS
STAGEx_MIN_TEMP
BANK 3 REGISTERS
MAX LEVEL
DETECTION
LOGIC
MIN LEVEL
DETECTION
LOGIC
Figure 35. Tracking the Minimum and Maximum Average Sensor Values
Table 14. Additional Information About Environmental Calibration and Adaptive Threshold Registers
Bit
Register
Location
Description
NEG_THRESHOLD_SENSITIVITY
Bank 2
Used in Equation 2. This value is programmed once at startup.
NEG_PEAK_DETECT
Bank 2
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the minimum average CDC value. If the output of the CDC gets within
the NEG_PEAK_DETECT percentage of the minimum average, only then is the minimum
average value updated.
POS_THRESHOLD_SENSITIVITY
Bank 2
Used in Equation 1. This value is programmed once at startup.
POS_PEAK_DETECT
Bank 2
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the maximum average CDC value. If the output of the CDC gets within
the POS_PEAK_DETECT percentage of the maximum average, only then is the maximum
average value updated.
STAGEx_OFFSET_LOW
Bank 2
Used in Equation 2. An initial value (based on sensor characterization) is programmed
into this register at startup. The AD7148 on-chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGEx_OFFSET_LOW_CLAMP value.
STAGEx_OFFSET_HIGH
Bank 2
Used in Equation 1. An initial value (based on sensor characterization) is programmed
into this register at startup. The AD7148 on-chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGEx_OFFSET_HIGH_CLAMP value.
STAGEx_OFFSET_HIGH_CLAMP
Bank 2
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
startup. The value in this register prevents a user from causing sensor output value to
exceed the expected nominal value.
Set to the maximum expected sensor response, maximum change in CDC output code.
STAGEx_OFFSET_LOW_CLAMP
Bank 2
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
startup. The value in this register prevents a user from causing sensor output value to
exceed the expected nominal value.
Set to the minimum expected sensor response, minimum change in CDC output code .
STAGEx_SF_AMBIENT
Bank 3
Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor
is not touched, as calculated using the slow FIFO.
STAGEx_HIGH_THRESHOLD
Bank 3
Equation 1 value.
STAGEx_LOW_THRESHOLD
Bank 3
Equation 2 value.
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