參數(shù)資料
型號: AD7148ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 17/57頁
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 16LFCSP
標準包裝: 1
類型: 電容性
觸摸面板接口: 2 線
輸入數(shù)/鍵: 8
分辨率(位): 16 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 250k
電壓基準: 內(nèi)部
電源電壓: 2.6 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP
包裝: 標準包裝
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 23 of 56
07
15
5-
0
32
CD
C
O
U
T
P
U
T
CO
DE
S
t
SENSOR 1 INT
ASSERTED
1
2
3
4
5
6
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
CHANGING ENVIRONMENTAL CONDITIONS
NOTES
1. INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
SENSOR 2 INT
ASSERTED
2. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
3. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
4. INITIAL STAGEx_LOW_THRESHOLD.
5. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
6. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
Figure 33. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 30, there are a number of FIFOs implemented
on the AD7148. These FIFOs are located in Bank 3 of the on-chip
memory. The slow FIFOs are used by on-chip logic to monitor
the ambient capacitance level from each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12]are the slow FIFO skip control
for full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient capacitance
value tracks the measured capacitance value read by the converter.
Slow FIFO update rate in full power mode is equal to
AVG_FP_SKIP × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4x107]
Slow FIFO update rate in low power mode is equal to
(AVG_LP_SKIP +1) × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) ×
4x107]/[(FF_SKIP_CNT +1 ) + LP_CONV_DELAY]
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate of 25 ms. AVG_FP_SKIP and AVG_LP_
SKIP are used to normalize the frequency of the samples going into
the FIFO, regardless of how many conversion stages are in a
sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. When using all eight conversion stages,
recommended values for these settings are
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = skip 0 samples
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL (Address 0x003[15:14])
controls whether the most recent CDC measurement goes into
the slow FIFO (slow filter) or not. The slow filter is updated
when the difference between the current CDC value and last
value pushed into the slow FIFO is greater than SLOW_FILTER_
UPDATE_LVL.
Equations for On-Chip Logic Stage High and Logic Stage Low Threshold Calculation
STAGEx_HIGH_THRESHOLD = STAGE_SF_AMBIENT +
4
_
HIGH
OFFSET
STAGEx
+
16
4
_
HIGH
OFFSET
STAGEx
HIGH
OFFSET
STAGEx
× POS_THRESHOLD_SENSITIVITY
(1)
STAGEx_LOW_THRESHOLD = STAGE_SF_AMBIENT +
4
_
LOW
OFFSET
STAGEx
+
16
4
_
LOW
OFFSET
STAGEx
LOW
OFFSET
STAGEx
× POS_THRESHOLD_SENSITIVITY
(2)
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