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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 60/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BC |
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AD6652
Channel Address
A4
A5
A6
A7
A8
A9
Rev. 0 | Page 60 of 76
Bit Wid
11
16
16
20
3
10
Register
RCF Control Register
BIST Signature for I Path
BIST Signature for Q Path
BIST Outputs to Accumulate
RAM BIST Control Register
Output Control Register
th
Comments
10:
9:
8:
7:
6:
5-4:
3-0:
BIST-I
BIST-Q
19-0:
2:
1:
0:
9:
5:
4-0:
RCF bypass BIST
RCF input select (own 0, other 1)
Program RAM bank 1/0
Use common exponent
Force output scale
Output format
nt 12 + 4
1x: Floating poi
point 8 + 4
01: Floating
00: Fixed point
Output scale
Number of outputs (counter value read)
D-RAM fail/pass
pass
C-RAM fail/
RAM BIST enable
Map RCF data to BIST registers
Output format
1: 16-bit I and 16-bit Q
I and 12-bit Q
0: 12-bit
Reserved, write to Logic 0
0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It can
be interpreted as values ranging from 0 to just under 2π. The
o the 16 MSBs of the 32-bit NCO
rrive at the final phase angle number
phase accumulator to a
used to compute the amplitude value.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the
channel. The bits are defined in this section. For details, see the
Numerically Controlled Oscillator section.
ular
16-bit phase offset is added t
Bits 8–7 of this register choose which one of the four
Pin_SYNC pins (A, B, C, or D) is used by the channel to initiate
channel start and frequency hop functions. These bits can also
be used to make timing adjustments to a channel.
Table 25 shows the bit logic state needed to select a partic
Pin_Sync.
Table 25. Bit Logic States for Sync Pins
0x88:8
0x88:7
0
0
0
1
1
0
1
1
Sync Pin Selected
A
B
C
D
Bit 6 of this register defines which ADC channel, A or B, is used
by the DDC channel being programmed. If this bit is low, then
nput Port A selected; if this bit is high, Input Port B is selected.
I
Bits 5–4 are reserved and must be written logic low.
e
m
ared.
it
-
equen-
e and amplitude dither
use of these features is
y
stage
to be bypassed. When this occurs, the data from Input Port A is
th of the channel and the data from Input
passed down the I pa
Port B is passed down the Q path of the channel. This allo
real filter to be performed on baseband I and Q data.
Ox89–0x8F: Unused
Unused.
0x90: rCIC2 Decimation 1 (M
rCIC2
1)
This register sets the decimation in the rCIC2 filter. The va
written to this reg
d
ws a
lue
ister is the decimation minus one. The rCIC2
ecimation can range from 1 to 4096, depending upon the
interpolation of the channel. The decimation must always be
greater than the interpolation.
Bit 3 determines whether or not the phase accumulator of th
NCO is cleared when a hop occurs. The hop can originate fro
either Pin_SYNC or Soft_SYNC. When this bit is set to 0, the
hop is phase-continuous and the accumulator is not cle
When this bit is set to 1, the accumulator is cleared to 0 before
begins accumulating the new frequency word. This is appropri
ate when multiple channels are hopping from different fr
cies to a common frequency.
Bits 2–1 control whether or not the phas
functions of the NCO are activated. The
determined by the system constraints. See the Numericall
Controlled Oscillator section for more information on the use
of dither. As usual, a logic high activates the function.
Bit 0 of this register allows the NCO frequency translation
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相關代理商/技術參數(shù) |
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| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
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| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
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