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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 28/76頁 |
| 文件大小： | 1839K |
| 代理商： | AD6652BC |
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AD6652
Clock Input Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensiti
to ACLK clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic perform-
ance characteristics. The AD6652 contains a clock duty cycle
stabilizer that re-times the nonsampling edge, providing a
internal clock signal
sta ilizing is engaged by setting DUTYEN to logic high. This
allo s a wide range of ACLK clock input duty cycles without
ting the performance of the AD6652 ADC stage.
Rev. 0 | Page 28 of 76
ve
n
with a nominal 50% duty cycle. Duty cycle
affec
crea
sam
the
low
quire and lock to the new rate.
DLL to ac
gh
the c
inpu
calculated with the following equation:
f
INPUT
) due only to aperture jitter (t
A
) can be
In the equation, the rms aperture jitter,
t
, represents the root-
sum square of all jitter sources, which include the clock inpu
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
t,
signal with digital noise. Low jitter,
llators make the best clock sources. If the
nal
last s
e power dissip
nal to its samp
th PDWN pin
ower-down m
w power dissi
tting down th
th ADC chann
ether either h
tog
d by the AD6652 front-end AD
g rate. Norma
e set to logic lo
e by setting bo
ion in power-d
eference buffers and biasing ne
. Both power-
or low for pro
igh
is propor-
uires that
placed in
gic high.
ed by
rks of
riven
.
ion
DC operation
he ADC can
PDWN pins t
n mode is ach
ow
pins must b
r ADC operat
pe
r maximum p
ould remain st
ical power co
uts remain ac
nsumption for
ADC Wake-Up Time
upling capacitors on REFT and REFB are discharged
de, and then must be recharged when
when entering standby mo
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode. Shorter standby
cycles result in proportionally shorter wake-up times. With
recommended 0.1 μF and 10 μF deco
REFB, it takes approximately 1 s to full
referenc
operatio
er savings, the
while in stan
ption of 1 m
while in stan
e ADC is 12 mW
th
LK and analo
mode, result
for the ADC.
mode, typical power
dby
.
put(s)
in a
he clock
If t
the
upling capacitors on REFT
y discharge the
and
e buffer decoupling capacitors, and 5 ms to restore full
n.
modulating the clock
crystal-controlled osci
ACLK clock is generated from another type of source (by
gating, dividing, or other methods), re-time it by the origi
clock at the
tep.
ADC Power-Down Mode
Th
ate
tio
lin
bo
s b
a p
od
Lo
pat
shu
e r
bo
els
Th duty cycle stabilizer uses a delay-locked loop (DLL) to
te the nonsampling edge. As a result, any changes to the
pling frequency require approximately 2 ms to 3 ms to al
Hi
speed, high resolution ADCs are sensitive to the quality of
lock input. The degradation in SNR at a given full-scale
t frequency (
SNR degradation
= 20 × log10 [1/2 ×
p
×
f
INPUT
×
t
A
]
A
To minimize clock jitter, treat the ACLK clock input as an
analog signal. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid
C
req
be
o lo
iev
two
e d
l A
w. T
th
down
Fo
sh
typ
inp
co
ow
atic
nsum
tive
AC
dby
W
g in
ing
The deco
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相關代理商/技術參數(shù) |
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|---|---|
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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