- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375235 > AD6652BC (Analog Devices, Inc.) 12-Bit, 65 MSPS IF to Baseband Diversity Receiver PDF資料下載
參數(shù)資料
| 型號(hào)： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機(jī) |
| 文件頁(yè)數(shù)： | 5/76頁(yè) |
| 文件大小： | 1839K |
| 代理商： | AD6652BC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)
AD6652
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Table 1.
Parameter
AVDD
VDD
VDDIO
T
AMBIENT
Rev. 0 | Page 5 of 76
Temp
Full
Full
Full
Test Level
IV
IV
IV
IV
Min
2.75
2.25
3.0
40
Typ
3.0
2.5
3.3
+25
Max
3.3
2.75
3.6
+85
Unit
V
V
V
°C
ADC DC SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, 1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 2.
Parameter (Conditions)
Temp
RESOLUTION
Full
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
Load Regulation @ 1.0 mA
Full
Output Voltage Error (0.5 V Mode)
Full
Load Regulation @ 0.5 mA
Full
INPUT REFERRED NOISE
Input Span = 1 V Internal
25°C
Input Span = 2 V Internal
25°C
ANALOG INPUT
Input Span = 1.0 V
Full
Input Span = 2.0 V
Full
Input Capacitance
Full
REFERENCE INPUT RESISTANCE
Full
MATCHING CHARACTERISTICS
Offset Error
Full
Gain Error
Full
Test Level
IV
IV
V
V
V
V
V
IV
IV
V
V
V
V
Min
12
Typ
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
±0.1
±0.1
Max
±35
Unit
Bits
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
k
% FSR
% FSR
ADC SWITCHING SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, 1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 3.
Parameter (Conditions)
Temp
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
Minimum Conversion Rate
Full
ACLK Period
Full
ACLK Pulse Width High
1
Full
ACLK Pulse Width Low
1
Full
DATA OUTPUT PARAMETERS
Wake-Up Time
2
Full
OUT-OF-RANGE RECOVERY TIME
Full
Test Level
IV
V
V
V
V
V
V
Min
65
15.4
6.2
6.2
Typ
ACLK/2
ACLK/2
2.5
2
Max
1
Unit
MSPS
MSPS
ns
ns
ns
ms
Cycles
1
Duty cycle stabilizer enabled.
2
Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6652PCB | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6816 | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| AD693(中文) | Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器) |
| AD7010ARS | MIL-spec connector accessory |
| AD7010 | CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。