tDD DATA VALID
參數(shù)資料
型號(hào)： AD6620ASZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 44/44頁(yè)
文件大?。?/td> 0K
描述： IC DGTL RCVR DUAL 67MSPS 80-PQFP
標(biāo)準(zhǔn)包裝： 500
接口： 并行/串行
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-PQFP（14x14）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
AD6620
–9–
REV. A
MICROPORT MODE0, READ
Timing is synchronous to CLK; MODE = 0.
tDD
DATA VALID
tHC
tSC
tHC
tZD
tHA
tRDY
ADDRESS VALID
tSAM
tZR
N
N+1
N+2
N+3
N+4
N
CLK1
WR2
RD2
CS3
D[7:0]
RDY1
A[2:0]
NOTES:
1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2 THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.
Figure 17. MODE0 Read Timing Requirements and Switching Characteristics
MICROPORT MODE0, WRITE
Timing is synchronous to CLK; MODE = 0.
DATA VALID
tHC
tSC
tHC
tSC
tHM
ADDRESS VALID
N
N+1
N+2
N+3
N*
CLK1
WR2
RD2
CS3
D[7:0]
RDY
A[2:0]
NOTES:
1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
RISING EDGE OF CLK "N+2".
2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.
tHA
tRDY
tSAM
Figure 18. MODE0 Write Timing Requirements and Switching Characteristics
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