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參數(shù)資料
| 型號： | AD6620ASZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 標準包裝： | 500 |
| 接口： | 并行/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-BQFP |
| 供應商設備封裝： | 80-PQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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AD6620
–34–
REV. A
DATA VALID
tSC
ADDRESS VALID
N
N+1
N+2
N+3
CLK1
R/W2
DS2
CS3
D[7:0]
DTACK
A[2:0]
tSAM
N+4
N
tHC
tDD
tHC
tZD
tHA
tDTACK
NOTES:
1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2 THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE
DTACK HIGH.
tSC
tZR
Figure 45. Mode 1 Read (MODE = VDD)
Mode = 1
If the MODE input is held high the interface is in Mode 1. In
Mode 1 the
RD signal becomes the data strobe (DS) and the
WR signal becomes a read/write (R/W) select signal. In this
tSC
N
N+1
N+2
N+3
tSAM
N*
tDTACK
tSC
CLK1
R/W2
DS2
CS3
D[7:0]
DTACK
A[2:0]
tHC
tDTACK
tSAM
tHM
tHA
NOTES:
1 ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE
DTACK HIGH.
*THE NEXT WRITE MAY BE INITIATED ON CLK, N*
DATA VALID
ADDRESS VALID
Figure 46. Mode 1 Write (MODE = VDD)
mode the
DTACK signal goes low when data is available during
a read or when data has been latched during a write. The
DTACK
signal stays low until the
DS signal is released.
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