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參數(shù)資料
| 型號： | AD5066BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V QD 16TSSOP |
| 標準包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 15µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
AD5066
Rev. A | Page 17 of 24
POWER-ON RESET
The AD5066 contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the POR
pin low, the AD5066 output powers up to 0 V; by connecting
the POR pin high, the AD5066 output powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31 to
DB28
DB27
DB26
DB25
DB24
DB23 to
DB20
DB10 to
DB19
DB9
DB8
DB4 to
DB7
DB3
DB2
DB1
DB0
X
0
1
0
X
PD1
PD0
X
DAC D
DAC C
DAC B
DAC A
Don’t
cares
Command bits (C2 to C0)
Address bits
(A3 to A0)—
don’t cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel
selection—set bit to 1 to select
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