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參數(shù)資料
| 型號： | AD5066BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V QD 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 15µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
AD5066
Rev. A | Page 20 of 24
AD5066 to 80C51/80L51 Interface
Figure 45 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,
RxD drives DIN on the AD5066, and a bit-programmable pin on
the port (P3.3) drives the SYNC signal. When data is to be
transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51
transmit data in 8-bit bytes only; thus, only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second,
third, and fourth write cycle is initiated to transmit the second,
third, and fourth byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5066 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5066*
SYNC
P3.3
SCLK
TxD
DIN
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
06845-
011
Figure 45. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
Figure 46 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is clocked into
the AD5066 on the falling edge of the SCLK.
AD5066*
SYNC
CS
DIN
SK
SCLK
SO
*ADDITIONAL PINS OMITTED FOR CLARITY.
MICROWIRE*
06845-
012
Figure 46. AD5066 to MICROWIRE Interface
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