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參數(shù)資料
| 型號： | AD5066BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V QD 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 15µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | * |
AD5066
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VDD
VREFB
VOUTC
VOUTA
VREFA
POR
16
15
14
13
12
11
10
9
DIN
GND
VOUTB
VREFC
VREFD
VOUTD
SCLK
AD5066
TOP VIEW
(Not to Scale)
LDAC
SYNC
CLR
06845-
004
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.
When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd
clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but
the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt, and the write sequence is ignored by the device.
3
V
DD
Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 F
capacitor in parallel with a 0.1 F capacitor to GND.
4
V
REFB
External Reference Voltage Input for DAC B.
5
V
REFA
External Reference Voltage Input for DAC A.
6
V
OUTA
Unbuffered Analog Output Voltage from DAC A.
7
V
OUTC
Unbuffered Analog Output Voltage from DAC C.
8
POR
Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying
this pin to V
DD powers the DAC outputs to midscale.
9
V
REFC
External Reference Voltage Input for DAC C.
10
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11
V
REFD
External Reference Voltage Input for DAC D.
12
V
OUTD
Unbuffered Analog Output Voltage from DAC D.
13
V
OUTB
Unbuffered Analog Output Voltage from DAC B.
14
GND
Ground Reference Point for All Circuitry on the Part.
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
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