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參數(shù)資料
| 型號： | A3PE-STARTER-KIT-2 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 60/162頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR A3PE1500 PROASIC3 |
| 產(chǎn)品變化通告： | Kit/Part Number Change 25/Jul/2012 |
| 標準包裝： | 1 |
| 系列： | ProASIC3 |
| 類型： | FPGA |
| 適用于相關產(chǎn)品： | A3PE1500 |
| 所含物品： | 板，電源，編程器 |
| 其它名稱： | 1100-1144 A3PE-STARTER-KIT |
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Datasheet Information
5-2
Revision 13
Revision 11
(continued)
Figure 2-11 AC Loading was updated to match tables in the "Summary of I/O
In Table 2-81 Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
37222).
Figure 2-47 FIFO Read and Figure 2-48 FIFO Write are new (SAR 34848).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" chapter: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from
the output buffer VCCI domain" and replaced with “Within the package, the VMV
plane biases the input stage of the I/Os in the I/O banks” (SAR 38322). The
datasheet mentions that "VMV pins must be connected to the corresponding
VCCI pins" for an ESD enhancement.
Revision 10
(March 2012)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in
the industry (SAR 34669).
The Y security option and Licensed DPA Logo were added to the "ProASIC3E
Ordering Information" section. The trademarked Licensed DPA Logo identifies
that a product is covered by a DPA counter-measures license from Cryptography
Research (SAR 34727).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-
voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG
interface" (SAR 34689).
The "Specifying I/O States During Programming" section is new (SAR 34699).
VCCPLL in Table 2-2 Recommended Operating Conditions 1 was corrected
from "1.4 to 1.6 V" to "1.425 to 1.575 V" (SAR 33851).
The TJ symbol was added to the table and notes regarding TA and TJ were
removed. The second of two parameters in the VCCI and VMV row, called "3.3 V
DC supply voltage," was corrected to "3.0 V DC supply voltage" (SAR 37227).
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to t
he "Spine
Architecture" section of the Global Resources chapter in the ProASIC3E
FPGA Fabric User's Guide (SAR 34735).
(example) (SAR 37109).
The typo related to the values for 3.3 V LVCMOS Wide Range in Table 2-17
corrected (SAR 37227).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics
section and tables were revised for clarification. They now state that the minimum
drive strength for the default software configuration when run in wide range is
±100 A. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 34763).
Revision
Changes
Page
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