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參數(shù)資料
| 型號： | A3PE-STARTER-KIT-2 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 24/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR A3PE1500 PROASIC3 |
| 產(chǎn)品變化通告： | Kit/Part Number Change 25/Jul/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProASIC3 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | A3PE1500 |
| 所含物品： | 板，電源，編程器 |
| 其它名稱： | 1100-1144 A3PE-STARTER-KIT |
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ProASIC3E Device Family Overview
1-6
Revision 13
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,
differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two
per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is
subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8
to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given
VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that
reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-3 on page 1-7).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PFA1X201J1 | 制造商:APEM 功能描述:Pushbutton,A3,latching,12V,red |
| A3PFA1X201J2 | 制造商:APEM 功能描述:Pushbutton,latching,12V,green |
| A3PFA1X201J3 | 制造商:APEM 功能描述:Pushbutton,latching,12V,amber |
| A3PFA1X201J4 | 制造商:APEM 功能描述:Pushbutton,A3,latching,12V,blue |
| A3PFA1X201K1 | 制造商:APEM 功能描述:Pushbutton,A3,latching 24V,red |
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