參數(shù)資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設備用戶指南掩模組L15Y - （二硅-增強的功能集）
文件頁數(shù)： 3/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV2
3
V01.04
01.Sep
2003
Corrected Table 0-1 Document References
Corrected Maskset number
Added Connectivity of NV bits in FCTL Register
(FTX512k4)
corrected
Table 5-1
and added XGATE Software Error
Interrupt
Added EROMCTL functionality
V01.05
22. Oct
2003
Added XGATE Channel ID’s to
Table 5-1
Aded 3.3V/5V Operation on PC/PD/PE5 and PE6
Added Pullup Devices on RESET/TEST and VREGEN Pin
Added ROMON/EROMON Description to
4.2 Chip
Configuration Summary
Removed Security Description
updated section
4.2 Chip Configuration Summary
V01.06
10. Nov
2003
updated section
4.2.5 Register visibility in Emulation
and Expanded modes
corrected XCLKS description
Added IQSTAT3 signal
Added SPI Master/Slave Mode Timing Characteristics
Renamed VDDX3/VSSX3 to VDDR2/VSSR2 and
VDDR/VSSR to VDDR1/VSSR1
Corrected several typos
Modiefied PD0-PD3 pin order
Added
Section 1.6 Detailed Register Map
BDM is visible on PPAGE=$FF at address $BF00-$BFFF
if bdm active
Figure 1-3
Modified XGATE Register Space $0380 - $03BF
Table
1-1
Added LQFP144 PCB recommendation
Figure 28-1
V01.07
V01.08
29. Jan
2004
Updated Voltage Regulator Electrical Characteristics
Added 3.3V I/O Characteristics
V01.09
10. Feb
2004
V01.10
28. Feb
2004
Added 3.3V ATD Characteristics
Added IrDA to SCI feature List
Added Internal Visibility Data to
Table 2-1
and to Signal
Description
V01.11
30. Mar
2004
Added
Figure 1-2
Logical to Global Address Mapping
Revision History
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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