參數(shù)資料
型號(hào)： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集）
文件頁(yè)數(shù)： 2/152頁(yè)
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV2
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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
DOCUMENT NUMBER
9S12XDP512DGV1/D
2
Revision History
Version
Number
V01.00
Revision
Date
02 Jun 03
Effective
Date
Author
Description of Changes
Initial Version
V01.01
22. Jul 03
Moved EWAIT function to PK7
Added ECLKX2 function to PE7
Moved TAGHI input to PE6
Moved TAGLO input to PE5
Corrected typo in figure 1-2
Added Freeze Mode to section 4
Modified PLL electrical parameters to TBD
Added four seperate interrupt vectors for PIT
Removed Regulator Current and Output Voltage Core and
Output Voltage PLL from Table 27-2
NVM Timing Characteristics Table A-11 maximum
f
NVMOSC
= 80MHz
Modified ATD Operating Characteristics Table A-8 and
A-9 to TBD
SPI Timing Characteristics set to TBD
Added XSRAM20K control register to memory map
V01.02
16.Aug 03
Added XSRAM20K interrupt vector
Included XSRAM20K Block Guide
Added XGATE Software Trigger to
Table 5-1
Addedsection
4.2.5Register visibilityinEmulationand
Expanded modes
Removed BDLC from
Table 5-1
V01.03
23. Aug
03
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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