參數(shù)資料
型號(hào)： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集）
文件頁數(shù)： 136/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV2
MC9S12XDP512 Device User Guide — V01.12
136
The loop bandwidth f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50.
ζ
= 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
C
=43kHz:
2
π
n f
C
K
Φ
The capacitance C
s
can now be calculated as:
The capacitance C
p
should be chosen in the range of:
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in
Figure A-2
. With each transition of the clock f
cmp
, the
deviation from the reference clock f
ref
is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise,voltage,temperatureandotherfactorscauseslightvariationsinthecontrolloopresultinginaclock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
Figure A-3
.
f
C
2
ζ
f
ref
------------------------------------------
π
ζ
1
ζ
2
+
+
1
10
------
f
C
f
C
< 100kHz
f
ref
4 10
-------------
ζ
0.9
=
(
)
;
<
→
<
n
f
VCO
f
ref
-------------
2
synr
1
+
(
)
=
=
= 20
R
----------------------------
2
π
20 43kHz
539.1Hz
(
)
--------------------------------------------
10.0k
=
=
=
C
s
2
ζ
2
π
f
C
R
---------------------
0.516
f
C
R
--------------
ζ
0.9
=
(
)
;
=
=
= 1.2nF = ~ 1.0nF
C
s
20
------
C
p
C
s
10
------
≤
≤
C
P
= 100pF
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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