參數(shù)資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設備用戶指南掩模組L15Y - （二硅-增強的功能集）
文件頁數(shù)： 114/152頁
文件大小： 1231K
代理商： 9S12XDP512DGV2
MC9S12XDP512 Device User Guide — V01.12
114
The total power dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be considered:
1.
Internal Voltage Regulator disabled
P
IO
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For R
DSON
is valid:
VOL
IOL
respectively
2.
Internal voltage regulator enabled
I
DDR
is the current shown in
Table A-9
and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
i
∑
P
IO
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
TJ
TA
PD
Θ
JA
(
)
+
=
TJ
TA
PD
Θ
JA
Junction Temperature, [
°
C
]
=
Ambient Temperature, [
°
C
]
=
Total Chip Power Dissipation, [W]
=
Package Thermal Resistance, [
°
C/W]
=
PD
PINT
PIO
+
=
PINT
Chip Internal Power Dissipation, [W]
=
PINT
IDD
VDD
IDDPLL
i
∑
VDDPLL
IDDA
+
VDDA
+
=
PIO
RDSON
IIOi
2
=
RDSON
------------;
=
RDSON
VDD5
----------------------------------- for outputs driven high
;
VOH
–
IOH
=
PINT
IDDR
VDDR
IDDA
VDDA
+
=
PIO
RDSON
IIOi
2
=
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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