![](http://datasheet.mmic.net.cn/230000/9S12T64AF16V1_datasheet_15574448/9S12T64AF16V1_43.png)
Central Processing Unit (CPU)
Instruction Set Overview
MC9S12T64Revision 1.1.1
MOTOROLA
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
43
INSSame as LEAS1,SP
IncrementSP;(SP)+1
SP
IDX
1B 81
Pf
INX
IncrementX;(X)+1
X
INH
08
O
INY
IncrementY;(Y)+1
Y
INH
02
O
JMP
opr16a
JMP
oprx0_xysppc
JMP
oprx9
,
xysppc
JMP
oprx16
,
xysppc
JMP[D,
xysppc
]
JMP[
oprx16
,
xysppc
]
JSR
opr8a
JSR
opr16a
JSR
oprx0_xysppc
JSR
oprx9
,
xysppc
JSR
oprx16
,
xysppc
JSR[D,
xysppc
]
JSR[
oprx16
,
xysppc
]
LBCC
rel16
Same as LBHS
Jump
Subroutineaddress
PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
REL
06 hh ll
05 xb
05 xb ff
05 xb ee ff
05 xb
05 xb ee ff
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
Jumptosubroutine
(SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
Subroutineaddress
PC
17 dd
16 hh ll
15 xb
15 xb ff
15 xb ee ff
15 xb
15 xb ee ff
SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
Long branch if C clear; if C=0, then
(PC)+4+rel
PC
Long branch if C set; if C=1, then
(PC)+4+rel
PC
Long branch if equal; if Z=1, then
(PC)+4+rel
PC
Long branch if
≥
0, signed
If N
⊕
V=0, then (PC)+4+rel
PC
Long branch if
>
0, signed
If Z | (N
⊕
V)=0, then (PC)+4+rel
PC
Long branch if higher, unsigned
If C | Z=0, then (PC)+4+rel
PC
Long branch if higher or same,
unsigned; If C=0, (PC)+4+rel
PC
Long branch if
≤
0, signed; if
Z | (N
⊕
V)=1, then (PC)+4+rel
PC
Long branch if lower, unsigned; if
C=1, then (PC)+4+rel
PC
Long branch if lower or same,
unsigned; If C | Z=1, then
(PC)+4+rel
PC
Long branch if
<
0, signed
If N
⊕
V=1, then (PC)+4+rel
PC
Long branch if minus
If N=1, then (PC)+4+rel
PC
Long branch if not equal to 0
If Z=0, then (PC)+4+rel
PC
Long branch if plus
If N=0, then (PC)+4+rel
PC
Long branch always
18 24 qq rr
LBCS
rel16
Same as LBLO
REL
18 25 qq rr
LBEQ
rel16
REL
18 27 qq rr
LBGE
rel16
REL
18 2C qq rr
LBGT
rel16
REL
18 2E qq rr
LBHI
rel16
REL
18 22 qq rr
LBHS
rel16
Same as LBCC
REL
18 24 qq rr
LBLE
rel16
REL
18 2F qq rr
LBLO
rel16
Same as LBCS
REL
18 25 qq rr
LBLS
rel16
REL
18 23 qq rr
LBLT
rel16
REL
18 2D qq rr
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
LBMI
rel16
REL
18 2B qq rr
LBNE
rel16
REL
18 26 qq rr
LBPL
rel16
REL
18 2A qq rr
LBRA
rel16
REL
18 20 qq rr
OPPP
LBRN
rel16
Longbranchnever
REL
18 21 qq rr
OPO
LBVC
rel16
LongbranchifVclear
If V=0,then (PC)+4+rel
PC
LongbranchifVset
If V=1,then (PC)+4+rel
PC
REL
18 28 qq rr
OPPP
(branch)
OPO
(no branch)
OPPP
(branch)
OPO
(no branch)
LBVS
rel16
REL
18 29 qq rr
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
– – – – – – – –
– – – – –
– –
– – – – –
– –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
F
Freescale Semiconductor, Inc.
n
.