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Central Processing Unit (CPU)
Addressing Modes
MC9S12T64Revision 1.1.1
MOTOROLA
Central Processing Unit (CPU)
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35
consecutive memory locations; the high byte is in the lowest address,
but does not have to be aligned to an even boundary.
All I/O and all on-chip peripherals are memory-mapped. No special
instruction syntax is required to access these addresses. On-chip
register and memory mapping are determined at the SoC level and are
configured during integration of the Core into the system.
Addressing Modes
AsummaryoftheaddressingmodesusedbytheCoreisgivenin
Table 3
below.
The operation of each of these modes is shown in detail in the HCS12 CORE
user guide.
Table 3 Addressing Mode Summary
Addressing Mode
Source Form
Abbreviation
Description
Inherent
INST
(no externally supplied
operands)
INST #opr8i
or
INST #opr16i
INH
Operands (if any) are in CPU registers.
Immediate
IMM
Operand is included in instruction stream; 8-bit or
16-bit size implied by context.
Direct
INST opr8a
DIR
Operand is the lower 8-bits of an address in the range
$0000–$00FF.
Operand is a 16-bit address.
Extended
INST opr16a
INST rel8
or
INST rel16
EXT
Relative
REL
Effective address is the value in PC plus an 8-bit or
16-bit relative offset value.
Indexed
(5-bit offset)
Indexed
(predecrement)
Indexed
(preincrement)
Indexed
(postdecrement)
Indexed
(postincrement)
Indexed
(accumulator offset)
Indexed
(9-bit offset)
INST oprx5,xysp
IDX
Effective address is the value in X, Y, SP, or PC plus a
5-bit signed constant offset.
Effective address is the value in X, Y, or SP
autodecremented by 1 to 8.
Effective address is the value in X, Y, or SP
autoincremented by 1 to 8.
Effective address is the value in X, Y, or SP. The value
is postdecremented by 1 to 8.
Effective address is the value in X, Y, or SP. The value
is postincremented by 1 to 8.
Effective address is the value in X, Y, SP, or PC plus
the value in A, B, or D.
Effective address is the value in X, Y, SP, or PC plus a
9-bit signed constant offset.
INST oprx3,–xys
IDX
INST oprx3,+xys
IDX
INST oprx3,xys–
IDX
INST oprx3,xys+
IDX
INST abd,xysp
IDX
INST oprx9,xysp
IDX1
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