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Central Processing Unit (CPU)
Instruction Set Overview
MC9S12T64Revision 1.1.1
MOTOROLA
Central Processing Unit (CPU)
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41
CPY#
opr16i
CPY
opr8a
CPY
opr16a
CPY
oprx0_xysppc
CPY
oprx9
,
xysppc
CPY
oprx16
,
xysppc
CPY[D,
xysppc
]
CPY[
oprx16
,
xysppc
]
DAA
CompareY
(Y)–(M:M+1)
or (Y)–imm
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
8D jj kk
9D dd
BD hh ll
AD xb
AD xb ff
AD xb ee ff
AD xb
AD xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
DecimaladjustA for BCD
18 07
OfO
DBEQ
abdxysp
,
rel9
Decrementandbranchifequalto0
(counter)–1
counter
if(counter)=0,thenbranch
Decrementandbranchifnotequalto0;
(counter)–1
counter;
if(counter)
≠
0,thenbranch
DecrementM;(M)–1
M
REL
(9-bit)
04 lb rr
PPP
(branch)
PPO
(no branch)
DBNE
abdxysp
,
rel9
REL
(9-bit)
04 lb rr
PPP
(branch)
PPO
(no branch)
DEC
opr16a
DEC
oprx0_xysppc
DEC
oprx9
,
xysppc
DEC
oprx16
,
xysppc
DEC[D,
xysppc
]
DEC[
oprx16
,
xysppc
]
DECA
DECB
DESSame as LEAS–1,SP
DecrementA;(A)–1
A
DecrementB;(B)–1
B
DecrementSP;(SP)–1
SP
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
IDX
73 hh ll
63 xb
63 xb ff
63 xb ee ff
63 xb
63 xb ee ff
43
53
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
1B 9F
Pf
DEX
DecrementX;(X)–1
X
INH
09
O
DEY
DecrementY;(Y)–1
Y
INH
03
O
EDIV
Extendeddivide,unsigned;32by16
to16-bit;(Y:D)
÷
(X)
Y;remainder
D
Extendeddivide,signed;32by16to
16-bit;(Y:D)
÷
(X)
Yremainder
D
Extended multiply and accumulate,
signed; (M
X
:M
X+1
)
×
(M
Y
:M
Y+1
)
+
(M~M+3)
M~M+3;16by16to32-bit
Extended maximum in D; put larger of
2
unsigned 16-bit values in D
MAX[(D), (M:M+1)]
D
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
Extended maximuminM; putlarger of
2
unsigned 16-bit values in M
MAX[(D), (M:M+1)]
M:M+1
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
Extended minimum in D; put smaller
of
2 unsigned 16-bit values in D
MIN[(D), (M:M+1)]
D
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
INH
11
ffffffffffO
EDIVS
INH
18 14
OffffffffffO
EMACS
opr16a
Special
18 12 hh ll
ORROfffRRfWWP
EMAXD
oprx0_xysppc
EMAXD
oprx9
,
xysppc
EMAXD
oprx16
,
xysppc
EMAXD[D,
xysppc
]
EMAXD[
oprx16
,
xysppc
]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1A xb
18 1A xb ff
18 1A xb ee ff
18 1A xb
18 1A xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
EMAXM
oprx0_xysppc
EMAXM
oprx9
,
xysppc
EMAXM
oprx16
,
xysppc
EMAXM[D,
xysppc
]
EMAXM[
oprx16
,
xysppc
]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1E xb
18 1E xb ff
18 1E xb ee ff
18 1E xb
18 1E xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
EMIND
oprx0_xysppc
EMIND
oprx9
,
xysppc
EMIND
oprx16
,
xysppc
EMIND[D,
xysppc
]
EMIND[
oprx16
,
xysppc
]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1B xb
18 1B xb ff
18 1B xb ee ff
18 1B xb
18 1B xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
– – – –
– – – –
– – – – – – – –
– – – – – – – –
– – – –
–
– – – – – – – –
– – – – –
– –
– – – – –
– –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
F
Freescale Semiconductor, Inc.
n
.