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Central Processing Unit (CPU)
Instruction Set Overview
MC9S12T64Revision 1.1.1
MOTOROLA
Central Processing Unit (CPU)
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39
BLE
rel8
Branchif
≤
0,signed;ifZ | (N
⊕
V)=1,
then(PC)+2+rel
PC
Branchiflower, unsigned; ifC=1,
then (PC)+2+rel
PC
Branchiflowerorsame, unsigned; if
C | Z=1,then (PC)+2+rel
PC
Branchif
<
0, signed; ifN
⊕
V=1,then
(PC)+2+rel
PC
Branchifminus; ifN=1,then
(PC)+2+rel
PC
Branch if not equal to 0; ifZ=0,then
(PC)+2+rel
PC
Branchifplus; ifN=0,then
(PC)+2+rel
PC
Branchalways
REL
2F rr
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
BLO
rel8
Same as BCS
REL
25 rr
BLS
rel8
REL
23 rr
BLT
rel8
REL
2D rr
BMI
rel8
REL
2B rr
BNE
rel8
REL
26 rr
BPL
rel8
REL
2A rr
BRA
rel8
REL
20 rr
PPP
BRCLR
opr8a
,
msk8
,
rel8
BRCLR
opr16a
,
msk8
,
rel8
BRCLR
oprx0_xysppc
,
msk8
,
rel8
BRCLR
oprx9
,
xysppc
,
msk8
,
rel8
BRCLR
oprx16
,
xysppc
,
msk8
,
rel8
BRN
rel8
Branchifbit(s)clear; if
(M)
(mask byte)=0,then
(PC)+2+rel
PC
DIR
EXT
IDX
IDX1
IDX2
REL
4F dd mm rr
1F hh ll mm rr
0F xb mm rr
0F xb ff mm rr
0F xb ee ff mm rr
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
Branchnever
21 rr
P
BRSET
opr8
,
msk8
,
rel8
BRSET
opr16a
,
msk8
,
rel8
BRSET
oprx0_xysppc
,
msk8
,
rel8
BRSET
oprx9
,
xysppc
,
msk8
,
rel8
BRSET
oprx16
,
xysppc
,
msk8
,
rel8
BSET
opr8
,
msk8
BSET
opr16a
,
msk8
BSET
oprx0_xysppc
,
msk8
BSET
oprx9
,
xysppc
,
msk8
BSET
oprx16
,
xysppc
,
msk8
BSR
rel8
Branch if bit(s) set; if
(M)
(mask byte)=0,then
(PC)+2+rel
PC
DIR
EXT
IDX
IDX1
IDX2
DIR
EXT
IDX
IDX1
IDX2
REL
4E dd mm rr
1E hh ll mm rr
0E xb mm rr
0E xb ff mm rr
0E xb ee ff mm rr
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
Setbit(s)inM
(M) | mask byte
M
4Cdd mm
1C hh ll mm
0C xb mm
0C xb ff mm
0C xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
Branchtosubroutine;(SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
(PC)+2+rel
PC
BranchifVclear; if V=0,then
(PC)+2+rel
PC
BranchifVset; if V=1,then
(PC)+2+rel
PC
Callsubroutineinexpandedmemory
(SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
(SP)–1
SP;(PPG)
M
SP
pg
PPAGEregister
subroutineaddress
PC
CompareAto B;(A)–(B)
07 rr
SPPP
BVC
rel8
REL
28 rr
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
BVS
rel8
REL
29 rr
CALL
opr16a
,
page
CALL
oprx0_xysppc
,
page
CALL
oprx9
,
xysppc
,
page
CALL
oprx16
,
xysppc
,
page
CALL[D,
xysppc
]
CALL[
oprx16
,
xysppc
]
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
4A hh ll pg
4B xb pg
4B xb ff pg
4B xb ee ff pg
4B xb
4B xb ee ff
gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP
CBA
INH
18 17
OO
CLCSame as ANDCC #$FE
Clear C bit
IMM
10 FE
P
CLISame as ANDCC#$EF
ClearI bit
IMM
10 EF
P
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – –
0 –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – –
– – – – – – – 0
– – – 0 – – – –
F
Freescale Semiconductor, Inc.
n
.