參數(shù)資料
型號： 950812CGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件頁數(shù)： 28/31頁
文件大?。?/td> 285K
代理商： 950812CGLF
6
ICS950812
0542H—04/08/05
Pin #
Name
0
1
PWD
Bit 7
-
Spread Enabled
Spread Spectrum Control
RW
OFF
ON
0
Bit 6
-
CPUCLKT(2:0)
Power down mode output level
0= CPU driven in power down
1= undriven
RW
HIGH
LOW
0
Bit 5
35
3V66_1/VCH_CLK/FS4**
VCH/66.66 Select
RW
66.66
48.00
0
Bit 4
53
CPU_STOP#*
Reflects value of pin
R
Stop
Active
X
Bit 3
34
PCI_STOP#*
Reflects value of pin at power up.
Also can be set.
RW
Stop
Active
X
Bit 2
39
FS3
Frequency Selection
RW
-
X
Bit 1
55
FS1
Frequency Selection
R
-
X
Bit 0
54
FS0
Frequency Selection
R
-
X
Note: For PCI_STOP# function, refer to table 3.
Type
Bit Control
Control Function
Affected Pin
BYTE
0
Pin #
Name
0
1
PWD
Bit 7
43
MULTSEL*
Reflects value of pin
R
-
x
Bit 6
-
CPUCLKT(2:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
RW
HIGH
LOW
0
Bit 5
45, 44
CPUCLKT2, CPUCLKC2
(see note)
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 4
49, 48
CPUCLKT1, CPUCLKC1
(see note)
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 3
52, 51
CPUCLKT0, CPUCLKC0
(see note)
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 2
45, 44
CPUCLKT2, CPUCLKC2
Output control
RW
Disable
Enable
1
Bit 1
49, 48
CPUCLKT1, CPUCLKC1
Output control
RW
Disable
Enable
1
Bit 0
52, 51
CPUCLKT0, CPUCLKC0
Output control
RW
Disable
Enable
1
Note:
Type
Bit Control
Control Function
Affected Pin
BYTE
1
CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
Pin #
Name
0
1
PWD
Bit 7
56
REF
1X or 2X Strength control
RW
1X
2X
0
Bit 6
18
PCICLK6
Output control
RW
Disable
Enable
1
Bit 5
17
PCICLK5
Output control
RW
Disable
Enable
1
Bit 4
16
PCICLK4
Output control
RW
Disable
Enable
1
Bit 3
13
**E_PCICLK3/PCICLK3
Output control
RW
Disable
Enable
1
Bit 2
12
PCICLK2
Output control
RW
Disable
Enable
1
Bit 1
11
**E_PCICLK1/PCICLK1
Output control
RW
Disable
Enable
1
Bit 0
10
PCICLK0
Output control
RW
Disable
Enable
1
Note:
BYTE
2
Control Function
Bit Control
PCICLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3.
Affected Pin
Type
Pin #
Name
0
1
PWD
Bit 7
38
48MHz_DOT
Output control
RW
Disable
Enable
1
Bit 6
39
48MHz_USB/FS3**
Output control
RW
Disable
Enable
1
Bit 5
7
PCICLK_F2 (see note)
Allow control of output with
assertion of PCI_STOP#.
RW
Freerun
Not
Freerun
0
Bit 4
6
PCICLK_F1 (see note)
Allow control of output with
assertion of PCI_STOP#.
RW
Freerun
Not
Freerun
0
Bit 3
5
PCICLK_F0 (see note)
Allow control of output with
assertion of PCI_STOP#.
RW
Freerun
Not
Freerun
0
Bit 2
7
PCICLK_F2
Output control
RW
Disable
Enable
1
Bit 1
6
PCICLK_F1
Output control
RW
Disable
Enable
1
Bit 0
5
PCICLK_F0
Output control
RW
Disable
Enable
1
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
BYTE
3
Control Function
Affected Pin
Bit Control
Type
相關(guān)PDF資料
PDF描述
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