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參數資料
| 型號： | 950812CGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件頁數： | 19/31頁 |
| 文件大?。?/td> | 285K |
| 代理商： | 950812CGLF |
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ICS950812
0542H—04/08/05
PD# Functionality
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CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the
de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C
Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-
assertion.
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
Power Down Assertion of Waveforms
0ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
25ns
50ns
CPU_STOP#
CPUCLKT(2:0)
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*Signal TS is CPUCLKT in Tri-State mode
相關PDF資料 |
PDF描述 |
|---|---|
| 08056C103JAT4A | General Specifications |
| 950812YGLFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950812YGT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950902DGLFT | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08056C103JAT7A | Separating plate, width: 0.8 mm, color: gray - TS-GSK |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 950812CGLFT | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 950812YFLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| 950812YGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| 950813 | 制造商:Weidmuller 功能描述:NEXT 74/55/16, 4GP, ST, ZINC -EA - Bulk |
| 9508131 | 制造商:Molex 功能描述: |
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