- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24864 > 950812CGLF (INTEGRATED DEVICE TECHNOLOGY INC) 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF資料下載
參數(shù)資料
| 型號(hào)： | 950812CGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 285K |
| 代理商： | 950812CGLF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
3
ICS950812
0542H—04/08/05
Pin Configuration (Continued)
PIN # PIN NAME
PIN TYPE
DESCRIPTION
29
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
30
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
31
GND
PWR
Ground pin.
32
VDD3V66
PWR
Power pin for the 3V66 clocks.
33
3V66_0/FS5**
I/O
Frequency select latch input pin / 3.3V 66.66MHz clock output.
34
PCI_STOP#*
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
35
3V66_1/VCH_CLK/FS4**
I/O
Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz
VCH clock output.
36
GND
PWR
Ground pin.
37
VDD48
PWR
Power pin for the 48MHz output.3.3V
38
48MHz_DOT
OUT
48MHz clock output.
39
48MHz_USB/FS3**
I/O
Frequency select latch input pin / 3.3V 48MHz clock output.
40
FS2
IN
Frequency select pin.
41
GND
PWR
Ground pin.
42
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
43
MULTSEL*
IN
3.3V LVTTL input for selection the current multiplier for CPU outputs
44
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
45
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
46
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
47
GND
PWR
Ground pin.
48
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
49
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
50
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
51
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
52
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
53
CPU_STOP#*
IN
Stops all CPUCLK besides the free running clocks
54
FS0
IN
Frequency select pin.
55
FS1
IN
Frequency select pin.
56
REF
OUT
14.318 MHz reference clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 08056C103JAT4A | General Specifications |
| 950812YGLFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950812YGT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950902DGLFT | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08056C103JAT7A | Separating plate, width: 0.8 mm, color: gray - TS-GSK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 950812CGLFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 950812YFLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| 950812YGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| 950813 | 制造商:Weidmuller 功能描述:NEXT 74/55/16, 4GP, ST, ZINC -EA - Bulk |
| 9508131 | 制造商:Molex 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。