
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-29
11:10
PSU_DITHER
R/W
0
Output format dither mode
00: no dithering
01: error dispersion (never reset pattern)
10: error dispersion (reset pattern at rst capture enable)
11: error dispersion (reset pattern every eld)
9:8
PSU_ALPHA
R/W
0
Output format alpha mode
00 = no alpha (alpha byte not written)
01 = alpha byte written, value from CKEY_ALPHA (offset 284)
10 = reserved
11 = reserved
setting 00 is ignored if size of alpha component is less than 8 bits
7:0
PSU_OPFMT
R/W
0
Output formats
08 (hex) = YUV 4:2:2, semi-planar
0B (hex) = YUV 4:2:2, planar
0F (hex) = RGB or YUV 4:4:4, planar
A9 (hex) = compressed 4/4/4 + (4 bit alpha)
AA (hex) = compressed 4/5/3 + (4 bit alpha)
AD (hex) = compressed 5/6/5
A0 (hex) = packed YUY2 4:2:2
A1 (hex) = packed UYVY 4:2:2
E2 (hex) = YUV or RGB 4:4:4 + (8 bit alpha)
E3 (hex) = VYU 4:4:4 + (8 bit alpha)
Offset 0x10 6304
Target Window Size
31:27
reserved
-
26:16
PSU_LSIZE
R/W
0
Line size
Used for horizontal cropping after scaling
0 = cropping disabled
1 = one pixel
15:11
reserved
-
10:0
PSU_LCOUNT
R/W
0
Line count
Used for vertical cropping after scaling
0 = cropping disabled
1 = one line
Video Output Address Generation Control Registers
Offset 0x10 6340
Target Base Address #1
31:28
reserved
-
27: 3
PSU_BASE1
R/W
Base address DMA #1
used depending on PSU_BAMODE setting
2:0
PSU_OFFSET1
R/W
Base address byte offset plane 1
bits dene pixel offset within multi pixel 64 bit words
(e.g. a 16bit pixel can be placed on any 16 bit boundary)
Offset 0x10 6344
Target Line Pitch #1
31:15
Unused
-
14: 3
PSU_PITCH1
R/W
Line pitch DMA #1, signed value (two’s complement)
used for all packed formats and for plane 1
2:0
Unused
-
Offset 0x10 6348
Target Base Address #2
Table 10: Video Input Processor (VIP) 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description