
2004 Jul 22
148
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
15.7.4
SUBADDRESS 8FH
Table 108 Status information scaler part; 8FH[7:0]; read only register
Note
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
15.7.5
SUBADDRESSES 90H AND C0H
Table 109 Task handling control; register set A [90H[7:6]] and B [C0H[7:6]]; note
1 Note
1. X = don’t care.
Table 110 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]]
BIT
I2C-BUS
STATUS BIT
D7
XTRI
status on input pin XTRI, if not used for 3-state control, usable as hardware ag for software use
D6
ITRI
status on input pin ITRI, if not used for 3-state control, usable as hardware ag for software use
D5
FFIL
status of the internal ‘FIFO almost lled’ ag
D4
FFOV
status of the internal ‘FIFO overow’ ag
D3
PRDON
copy of bit DPROG, can be used to detect power-up and start-up fails
D2
ERROF
error ag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conicts, e.g. if output data rate is much too low and all
internal FIFO capacity used
D1
FIDSCI
status of the eld sequence ID at the scalers input
D0
FIDSCO
status of the eld sequence ID at the scalers output, scaler processing dependent
EVENT HANDLER CONTROL
CONTROL BITS D7 AND D6
CONLH
OFIDC
Output eld ID is eld ID from scaler input
X
0
Output eld ID is task status ag, which changes every time a selected task
is activated (not synchronized to input eld ID)
X1
Scaler SAV/EAV byte bit D7 and task ag = 1, default
0X
Scaler SAV/EAV byte bit D7 and task ag = 0
1
X
EVENT HANDLER CONTROL
CONTROL BITS D5 TO D3
FSKP2
FSKP1
FSKP0
Active task is carried out directly
0
1 eld is skipped before active task is carried out
0
1
... elds are skipped before active task is carried out
...
6 elds are skipped before active task is carried out
1
0
7 elds are skipped before active task is carried out
1