- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36339 > 935273916518 (NXP SEMICONDUCTORS) COLOR SIGNAL DECODER, PBGA156 PDF資料下載
參數(shù)資料
| 型號： | 935273916518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, LEAD FREE, PLASTIC, MS-034, SOT-472-1, BGA-156 |
| 文件頁數(shù)： | 152/178頁 |
| 文件大小： | 988K |
| 代理商： | 935273916518 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁當(dāng)前第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁
2004 Jul 22
75
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
9.5.2
X PORT CONFIGURED AS INPUT
If the data input mode is selected at the expansion port,
then the scaler can select its input data stream from the
on-chip video decoder, or from the expansion port
(controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial
Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes,
or raw samples from an external ADC may be input (see
also bits FSC[2:0] 91H[2:0]). The input stream must be
accompanied by an external clock (XCLK), qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes
according to ITU 656 are also accepted. The protection
bits are not evaluated.
XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]]
and XDV[1:0] 92H[5:4]).
The trigger events on XRH (rising/falling edge) and XRV
(rising/falling/both edges) for the scalers acquisition
window are defined by XDV[1:0] 92H[5:4] and
XDH[92H[2]]. The signal polarity of the qualifier can also
be defined (bit XDQ[92H[1]]). Alternatively to a qualifier,
the input clock can be applied to a gated clock (clock gated
with a data qualifier, controlled by bit XCKS[92H[0]]).
In this event, all input data will be qualified.
As the VBI data slicer may have different requirements for
its input reference signals from X port XRV, XRH, XDQ,
XCLK and XPD7 to XPD0, a second set of parameters is
available for defining the meaning of the X port input
signals and polarities for the VBI data slicer input path.
These bits are defined in subaddresses 81H and 82H.
9.6
Image port (I port)
The image port transfers data from the scaler as well as
from the VBI data slicer, if selected (maximum 33 MHz).
The reference clock is available at the ICLK pin, as an
output, or as an input (maximum 33 MHz). As output, ICLK
is derived from the line-locked decoder or expansion port
input clock. The data stream from the scaler output is
normally discontinuous. Therefore valid data during a
clock cycle is accompanied by a data qualifying (data
valid) flag on pin IDQ. For pin constrained applications the
IDQ pin can be programmed to function as a gated clock
output (bit ICKS2[80H[2]]).
The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), such as the related FIFO structures.
However the physical data stream at the image port is only
16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to
HPD0 are used for chrominance data. The four bytes of
the Dwords are serialized in words or bytes.
Available formats are as follows:
Y-C
B-CR 4:2:2
Y-CB-CR 4:1:1
Raw samples
Decoded VBI data.
For handshake with the receiving VGA controller, or other
memory or bus interface circuitry, F, H and V reference
signals and programmable FIFO flags are provided. The
information is provided on pins IGP0, IGP1, IGPH and
IGPV. The functionality on these pins is controlled via
subaddresses 84H and 85H.
VBI data is collected over an entire line in its own FIFO,
and transferred as an uninterrupted block of bytes.
Decoded VBI data can be signed by the VBI flag on pin
IGP0 or IGP1.
As scaled video data and decoded VBI data may come
from different and asynchronous sources, an arbitration
scheme is needed. Normally the VBI data slicer has
priority.
The image port consists of the pins and/or signals, as
listed in Table 33.
For pin constrained applications, or interfaces, the relevant
timing and data reference signals can also get encoded
into the data stream. Therefore the corresponding pins do
not need to be connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relationship to the
ITU-R BT.656 (D1) recommendation, where possible.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935273916557 | COLOR SIGNAL DECODER, PBGA156 |
| 935268460118 | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5 |
| 935268459115 | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5 |
| 935268459118 | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5 |
| 935268459125 | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935275527134 | 制造商:NXP Semiconductors 功能描述:IC BUS SWITCH OCTAL QUAD 20TSSOP |
| 935277864112 | 制造商:NXP Semiconductors 功能描述:IC CPU |
| 935278818112 | 制造商:NXP Semiconductors 功能描述:LCD DRVR 20DIGIT 2.5V/3.3V/5V 56-Pin VSO Tube |
| 935280517132 | 制造商:NXP Semiconductors 功能描述:IC TRANSLATING BUFFER 6XSON |
| 935281751112 | 制造商:NXP Semiconductors 功能描述:IC BUFFER/DVR 16BIT 3ST 48TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。