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參數資料
| 型號： | 935272706551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數： | 8/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706551 |
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2004 May 18
16
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
8
FUNCTIONAL DESCRIPTION
This triple high-speed 8-bit ADC is designed to convert
RGB/YUV signals coming from an analog source into
digital data used by a LCD driver (pixel clock up to
270 MHz with analog source) or projections systems.
8.1
Power management
It is possible to put the TDA8754 in standby mode by
setting bit STBY = 1 or to put the whole device in power-
down mode by setting pin PWD to HIGH level.
8.1.1
STANDBY MODE
In standby mode, the status of the blocks is as follows:
Activity detection, I2C-bus slave, sync separator and
SOG are still active
Pixel counter, ADCs, demultiplexers, AGC and clamp
cells are inactive
Output buffers to the RGB block (RGB 0 to 7, CKDATA,
DEO, HSYNCO and VSYNCO) are in high-impedance
state
Output HPDO is still active
Output buffers (ROR, BOR, GOR, CKREFO, CSYNCO,
CLPO and FIELDO) are in a LOW-level state.
8.1.2
POWER-DOWN MODE
In power-down mode the status of the blocks is as follows:
All digital inputs and outputs are in high-impedance
state
All blocks are inactive (I2C-bus, activity detection, ADCs,
etc.)
Analog output is left uncontrolled
I2C-bus is left in high-impedance state.
8.2
Analog video input
The RGB/YUV video inputs are externally AC coupled and
are internally DC polarized. The synchronization signals
are also used by the device as input for the internal PLL
and the automatic clamp.
8.2.1
ANALOG MULTIPLEXERS
The TDA8754 has two analog inputs (RGB input 1 and
RGB input 2) selectable via the I2C-bus.
The sync management can be achieved in several ways:
Choice between two analog inputs HSYNC and two
analog inputs VSYNC
Choice between two analog inputs CHSYNC
Choice between two analog inputs SOG.
8.2.2
ACTIVITY DETECTION
When a signal is connected or disconnected on
pins HSYNC1(2), CHSYNC1(2), VSYNC1(2) and
SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is
set to HIGH to advise the user of a change. Bit HPDO is
set to logic 0 and pin HPDO is set to LOW when register
ACTIVITY2 has been read.
When the synchronization pulse on pin SOG is 3-level, the
system will automatically be able to detect that a 3-level
sync is present and will force bit 3LEVEL to logic 1. It is
possible to disable this function with bit FTRILEVEL.
When an interlaced signal is detected, bit ACFIELD is set
to logic 1. When the signal detected is progressive, this bit
is set to logic 0. Any change in this bit results into setting
bit HPDO = 1 and pin HPDO = HIGH.
A field detection unit is available on pin FIELDO which
output is given by the sync separator. The field identity is
given by pin FIELDO. This pin gives the field of interlaced
signal input.
An automatic polarity detection is also available on
pins HSYNC1(2), VSYNC1(2) and CHSYNC1(2). The
output on pin HPDO is not affected by the change of
polarity of these inputs.
8.2.3
ADC
The three ADCs are designed to convert R, G and B
(or Y, U and V) signals at a maximum frequency of
270 Msps. The ADC input range is 1 V (p-p) full-scale and
the pipeline delay is 2 ADC clock cycles from the input
sampling to the data output.
The reference ladders regulators are integrated.
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