參數(shù)資料
型號(hào)： 935272706551
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 40/61頁(yè)
文件大?。?/td> 326K
代理商： 935272706551
2004 May 18
45
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
Data timing; 10 pF load; see Fig.4
td(o)
output delay
4
5.2
ns
th(o)
output hold time
1.9
ns
tsu(o)
output setup time
6ns
LV-TTL digital inputs and outputs
INPUT PINS CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK
AND
CLP
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2.0
VCCD
V
OUTPUT PINS
RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO,
HSYNCO, VSYNCO, FIELDO, CLPO, CKREFO AND CSYNCO
VOL
LOW-level output voltage
IOH =1mA
0.4
V
VOH
HIGH-level output voltage
IOL = 1 mA
2.4
V
Data clock output
OUTPUT PIN
CKDATA
fCKDATA(max)
maximum buffer frequency
140
MHz
Data outputs
OUTPUT PINS
RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO AND CSYNCO
fdata(max)
maximum buffer frequency
70
MHz
Hsync inputs
INPUT PINS HSYNC1, HSYNC2, CHSYNC1 AND CHSYNC2
tW(Hsync)(min)
minimum pulse width
250
ns
tW(Hsync)(max)
maximum pulse width
in % of total horizontal line
20
%
SOG inputs
INPUT PINS SOGIN1 AND SOGIN2
Vsync(G)
sync-on-green pulse amplitude
150
mV
Vsync(G)
high/low differential amplitude of
3-level pulse
20
%
I2C-bus (fast mode; 5 V tolerant)
PINS SCL AND SDA
fSCL
clock frequency
400
kHz
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2.0
5.5
V
Cb
capacitive load
400
pF
Thermal characteristics
Rth(j-c)
thermal resistance from junction
to case
LQFP144 package
8.1
8.5
°C/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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