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參數(shù)資料
| 型號： | 935272706551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 21/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706551 |
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2004 May 18
28
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.6
SOG register
Table 22 SOG (09h) bit allocation
Table 23 SOG (09h) bit description
5
0
1
1.005
6
0
1
0
1.006
7
1
1.007
BIT
7
6
5
4
3210
Symbol
DO
UP
FTRILEVEL
STRILEVEL
CKREFS
SOGSEL
SOGI1
SOGI0
Default
0
0001
BIT
SYMBOL
DESCRIPTION
7
DO
test bit for forcing charge pump current down
0 = default value
1 = forcing down
6
UP
test bit for forcing charge pump current up
0 = default value
1 = forcing up
5
FTRILEVEL
denes the 3-level function mode
0 = automatic 3-level
1 = level selection with bit STRILEVEL
4
STRILEVEL
forces the state of 3-level function
0 = not 3-level mode
1 = 3-level mode
3
CKREFS
enables the PLL Ckref signal to be selected
0 = same as input
1 = input inverted
2
SOGSEL
enables the reference PLL between HSYNC input and SOG input to be selected
0 = HSYNC input
1 = SOG input
1 to 0
SOGI[1:0]
denes the SOG charge pump current; values are given in % of sync pulse/line length
00 = 14.8 % maximum (TV standards) and non-VESA standards
01 = 12.6 % maximum (all standards)
10 = 8.6 % maximum (HDTV standards) and non-VESA standards
11 = 0 test mode
DECIMAL VALUE
FR2
FR1
FR0
FINE STEPS OF GAIN ADC
FG2
FG1
FG0
FB2
FB1
FB0
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