參數(shù)資料
型號： 935272706551
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁數(shù)： 18/61頁
文件大?。?/td> 326K
代理商： 935272706551
2004 May 18
25
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.3
Offset registers (R, G and B)
The offset registers contain a 9-bit value which controls the clamp level for the RGB channels. The 8 LSBs are in the
offset registers and the 1 MSB is in the coarse gain control register. The relationship between the programming code and
the level of the clamp code is given in Table 15. The default value is: clamp code = 0 and ADC output = 0.
Table 13 Offset registers (00h, 03h, 06h) bit allocation
Table 14 Offset registers (00h, 03h, 06h) bit description
Table 15 Coding for clamp level and ADC output
REGISTER
76543210
OFFSETR (00h)
OR7
OR6
OR5
OR4
OR3
OR2
OR1
OR0
OFFSETG (03h)
OG7
OG6
OG5
OG4
OG3
OG2
OG1
OG0
OFFSETB (06h)
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
Default
00000000
BIT
SYMBOL
DESCRIPTION
OFFSETR (address: 00h)
7 to 0
OR[7:0]
offset R channel; LSB in this register and MSB bit OR8 in register COARSER
OFFSETG (address: 03h)
7 to 0
OG[7:0]
offset G channel; LSB in this register and MSB bit OG8 in register COARSEG
OFFSETB (address: 06h)
7 to 0
OB[7:0]
offset B channel; LSB in this register and MSB bit OB8 in register COARSEB
HEX
VALUE
OR8
OR7
OR6
OR5
OR4
OR3
OR2
OR1
OR0
CLAMP CODE
(DECIMAL)
ADC OUTPUT
(CODE TRANSITION)
OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0
OB8
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
1 E9
111101000
24
24/23
1 EA
111101001
23
23/22
:
::
1 FF
111111111
1
1/0
0 00
000000000
0
0/1
0 01
000000001
+1
1/2
:
::
0 3F
000111111
63
63/64
0 40
001000000
64
64/65
:
::
0 78
001111000
120
120/121
0 79
001111001
121
121/122
:
::
0 80
010000000
128
128/129
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