參數(shù)資料
型號(hào)： 935272706551
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 24/61頁(yè)
文件大?。?/td> 326K
代理商： 935272706551
2004 May 18
30
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
Table 28 Phase registers bits
Table 29 VCO gain control
9.9
PLL divider registers
Table 30 DIVMSB (0Ch) bit allocation
Table 31 DIVMSB (0Ch) bit description
PA4
PA3
PA2
PA1
PA0
PHASE SHIFT (deg)
00000
0
00001
11.25
:::::
:
11110
337.50
11111
348.75
VCO2
VCO1
VCO0
VCO GAIN
(MHz/V)
PIXEL CLOCK FREQUENCY
(MHz)
0
13
12 to 22
0
1
30
22 to 45
0
1
0
60
45 to 62
0
1
60
62 to 85
1
0
105
85 to 120
1
0
1
105
120 to 176
1
0
135
176 to 270
1
no oscillation
BIT
76543210
Symbol
CKEXT
SCH
CKREFO
EPSI1
EPSI0
DI11
DI10
DI9
DI8
Default
00000110
BIT
SYMBOL
DESCRIPTION
7
CKEXT
external clock selection
0 = internal PLL
1 = external clock
6
SCH
CKREFO
shift of pixel counter reference (Ckref) with one clock pixel period
0 = not active
1 = active
5 to 4
EPSI[1:0]
enables the resynchronization edge of CKREFO to be selected; they are test bits
00 = default value for proper operation
3 to 0
DI[11:8]
PLL divider ratio. These are the 4 MSBs of the 12-bit value. See Table 34.
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