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參數(shù)資料
| 型號(hào)： | 935272706551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 39/61頁 |
| 文件大小： | 326K |
| 代理商： | 935272706551 |
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2004 May 18
44
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
Ptot
total power dissipation
1.0
1.3
W
P
power dissipation
power-down mode
10
mW
standby mode
120
mW
R, G and B ampliers
RGB INPUTS: PINS RIN1, GIN1, BIN1, RIN2, GIN2 AND BIN2
Vi(p-p)
input voltage range
(peak-to-peak value)
0.5
1.0
V
Ii
input current
40
+40
A
Ci
input capacitance
3
pF
Ri
input resistance
50
k
AMPLIFIERS
B
bandwidth
3 dB; Tamb =25 °C
700
MHz
Gc
coarse gain
minimum coarse gain; code = 32
0
dB
maximum coarse gain;
code = 95
6
dB
G/T
amplier gain stability variation
with temperature
minimum coarse gain; code = 32
2
%
GE(rms)
full-scale channel-to-channel
matching (RMS value)
minimum coarse gain; code = 32
2.5
%
R, G and B clamp
Nclamp
clamp level accuracy
fCLK = 25MHz, clamp code = 20
1
LSB
Phase-Locked Loop (PLL)
PLL; see Table 69
JPLL(p-p)
long term PLL phase jitter
(peak-to-peak value)
fclk = 270 MHz; DR = 2160
390
480
ps
DR
divider ratio
100
4095
fPLL
output clock frequency
10
270
MHz
fref
reference clock frequency
15
150
kHz
step
phase drift
2
step
step
phase shift step
11.25
deg
Analog-to-Digital Converters (ADCs); minimum coarse gain
fs(max)
maximum sampling frequency
270
MHz
INL
integral non-linearity
fclk = 270 MHz; fi = 10 MHz
±0.6
±1.3
LSB
DNL
differential non-linearity
fclk = 270 MHz; fi = 10 MHz
±0.25 ±0.6
LSB
ENOB
effective number of bits
fclk = 270 MHz; fi = 10 MHz
7.6
bits
αct
crosstalk
fclk = 270 MHz
45
dB
S/N
signal-to-noise ratio
fclk = 270 MHz; fi = 10 MHz
48
dB
SFDR
spurious free dynamic range
fclk = 270 MHz; fi = 10 MHz
48
55
dB
THD
total harmonic distortion
fclk = 270 MHz; fi = 10 MHz
-55
48
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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