參數(shù)資料
型號(hào)： 90E36ERGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 3/75頁(yè)
文件大?。?/td> 904K
代理商： 90E36ERGI
90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Pin Description
11
August 24, 2011
CF2
26
O
LVTTL
CF2: (all-phase-sum total) Reactive/ Apparent Energy Pulse Output
The output of this pin is determined by the CF2varh bit (b7, MMode0) and the CF2ESV bit
CF3
27
O
LVTTL
CF3: (all-phase-sum total) Active Fundamental Energy Pulse Output
CF4
28
O
LVTTL
CF4: (all-phase-sum total) Active Harmonic Energy Pulse Output
WarnOut
29
O
LVTTL
WarnOut: Fatal Error Warning
This pin is asserted high when there is metering related parameter checksum error. Other-
wise this pin stays low. Refer to 6.2.2 IRQ and WarnOut Signal Generation.
IRQ0
30
O
LVTTL
IRQ0: Interrupt Output 0
This pin is asserted when one or more events in the SysStatus0 register (01H) occur. It is
deasserted when there is no bit set in the SysStatus0 register (01H).
In Detection mode, the IRQ0 is used to indicate the output of current detector. The IRQ0
state is cleared when entering or exiting Detection mode.
IRQ1
31
O
LVTTL
IRQ1: Interrupt Output 1
This pin is asserted when one or more events in the SysStatus1 register (02H) occur. It is
deasserted when there is no bit set in the SysStatus1 register (02H).
In Detection mode, the IRQ1 is used to indicate the output of current detector. The IRQ1
state is cleared when entering or exiting Detection mode.
PM0
PM1
33
34
I
LVTTL
PM1/0: Power Mode Configuration
These two pins define the power mode of 90E36. Refer to Table-2.
DMA_CTRL
36
I
LVTTL
DMA_CTRL: DMA Enable
DMA is started when this pin is asserted.
DMA is stopped when this pin is deasserted. Refer to 4 SPI / DMA Interface.
CS
37
B
LVTTL
CS: Chip Select (Active Low)
In SPI mode, this pin must be driven from high to low for each read/ write operation, and
maintain low for the entire operation.
In DMA mode, this pin is asserted during data transmission. Refer to 4 SPI / DMA Interface.
SCLK
38
B
LVTTL
SCLK: Serial Clock
This pin is used as the clock for the SPI/DMA interface. Refer to 4 SPI / DMA Interface.
SDO
39
B
LVTTL
SDO: Serial Data Output
This pin is used as the data output for the SPI mode and input for the DMA mode. Refer to 4
SDI
40
B
LVTTL
SDI: Serial Data Input
This pin is used as the data input for the SPI mode and output for the DMA mode. Refer to 4
TEST
32
I
LVTTL
This pin should be always connected to DGND in system application.
NC
35, 45, 46
NC: These pins should be left open.
Table-1 Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
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參數(shù)描述
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90E3-SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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90E9A 制造商:NDK 制造商全稱:NDK 功能描述:crystal filter that supports surface mounting.
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