參數(shù)資料
型號(hào)： 90E36ERGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 22/75頁(yè)
文件大小： 904K
代理商： 90E36ERGI
90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
SPI / DMA Interface
29
August 24, 2011
4.3
MASTER MODE: DMA
The interface is defined to connect with various DSP processors for
ADC samples dumping.
For DMA configure please refer to DMACtrl register definition in 6.2
The interface works in Master mode when the DMA_CTRL pin is
pulled high by the external device. In Master mode, registers in 90E36
cannot be accessed. The dump transaction can be stopped by the exter-
nal device via pulling the DMA_CTRL pin to low at any time.
Figure-13 shows a connection between 90E36 and a DSP processor
where 90E36 acts as the master.
4.3.1
DMA BURST TRANSFER FOR ADC SAMPLING
When the DMA_CTRL pin changes from low to high, the voltage and
current channel ADC samples (after decimation and frequency compen-
sation) are dumped out serially through the interface with SCLK fre-
quency defined by the CLK_DIV[3:0] bits (b3~0, DMACtrl).
When the 90E36 detects that the DMA_CTRL pin is de-asserted, it
stops the DMA transaction after the current sample has been sent.
Clock Dividing Ratio
The SCLK frequency of SPI interface is defined by the CLK_DIV[3:0]
bits (b3~0, DMACtrl) as the following equation:
Here fsys_clk means system’s oscillator frequency.
Interface Direction
In DMA mode, the interface direction of SDI/SDO pins are normally
defined as Figure-13. But the direction also can be swapped by configur-
ing the PIN_DIR_SEL bit (b8, DMACtrl).
ADC Channel Selection
Internally, the 90E36 has 7 ADC channels. The user can select which
channel’s samples to be dumped out via configuring the ADC_CH_SE
L[15:9] bits (b15~9, DMACtrl).
Each bit of the 7-bit field ADC_CH_SEL enables the data dumping
for one ADC channel. Set ‘1’ to a bit enables the dump of the corre-
sponding ADC channel samples.
Clock Modes
Four clock modes are defined in master mode according to the
CLK_DRV bit (b4, DMACtrl) and CLK_IDLE bit (b5, DMACtrl) configura-
tion as the following diagram shows.
Figure-16 Clock Mode0 (CLK_DRV=0, CLK_IDLE=0) and Mode1 (CLK_DRV=0, CLK_IDLE=1)
2
+
2
*
CLK_DIV
f
=
f
sys_clk
SCLK
CLOCK Cycle #
SCLK
(CLK_IDLE=0)
SCLK
(CLK_IDLE=1)
SDI/SDO
CS
123
4
N-2
N
N-1
相關(guān)PDF資料
PDF描述
90MMCX-S50-0-51/111 MMCX CONNECTOR, JACK
91-21SUBC/S400-A6/TR10 T-3/4 SINGLE COLOR LED, BLUE, 1.9 mm
91-21SURC/S530-A3/TR7 T-3/4 SINGLE COLOR LED, BRILLIANT RED, 1.9 mm
91-21SURC/S530-A3/TR9 T-3/4 SINGLE COLOR LED, BRILLIANT RED, 1.9 mm
91-21USRC/S530-A4/F7 T-3/4 SINGLE COLOR LED, DARK RED, 1.9 mm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
90E36ERGI8 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel
90E3-SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
90E46EMGI 功能描述:計(jì)量片上系統(tǒng) - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
90E46EMGI8 制造商:Integrated Device Technology Inc 功能描述:Energy Metering SoC 100-Pin TQFP 制造商:Integrated Device Technology Inc 功能描述:100-PIN TQFP - Tape and Reel
90E9A 制造商:NDK 制造商全稱:NDK 功能描述:crystal filter that supports surface mounting.
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*