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參數(shù)資料
| 型號(hào)： | 908E625 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
| 中文描述： | 綜合四半僅符合電源橋，嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 42/48頁 |
| 文件大?。?/td> | 615K |
| 代理商： | 908E625 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
42
908E625
TYPICAL APPLICATIONS
FACTORY TRIMMING AND CALIBRATION
system has to be powered up providing V
SUP
(see
Figure 24
).
Figure 24. Normal Monitor Mode Circuit
Table 12
summarizes the possible configurations and the
necessary setups.
MM908E625
RST_A
RST
IRQ_A
IRQ
VDD
VSS
VSUP[1:3]
GND[1:2]
PTC4/OSC1
PTB3/AD3
PTB4/AD4
PTA0/KBD0
PTA1/KBD1
MAX232
10k
RS232
DB-9
1
3
C1+
C1-
4
5
C2+
C2-
7
8
2
3
5
V
CC
GND
16
15
2
V+
V-
6
1μF
+
1μF
+
+
1μF
1μF
+
+
1μF
2
1
3
6
5
4
74HC125
74HC125
9.8304MHz CLOCK
V
DD
V
DD
DATA
CLK
V
DD
10k
10k
10k
V
DD
V
TST
V
SUP
47μF
+
100nF
10
9
T2
OUT
R2
IN
T2
IN
R2
OUT
EVDD
4.7μF
100nF
VREFL
VDDA
EVSS
VREFH
VSSA
Table 12. Monitor Mode Signal Requirements and Options
Mode
IRQ RST
Reset
Vector
Serial
Communication
Mode
Selection
ICG
COP
Normal
Request
Timeout
Communication Speed
PTA0
PTA1
PTB3
PTB4
External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
V
TST
V
DD
X
1
0
0
1
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
Forced
Monitor
V
DD
V
DD
$FFFF
(blank)
1
0
X
X
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
GND
ON
disabled
disabled
—
Nominal
1.6MHz
Nominal
6300
User
V
DD
V
DD
not $FFFF
(not blank)
X
X
X
X
ON
enabled
enabled
—
Nominal
1.6MHz
Nominal
6300
Notes
1.
2.
3.
4.
5.
PTA0 must have a pullup resistor to V
DD
in monitor mode
External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1
Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
X = don’t care
V
TST
is a high voltage V
DD
+ 3.5V
≤
V
TST
≤
V
DD
+ 4.5V
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| 908E625_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
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