
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
908E625
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
INTERRUPT FLAG REGISTER (IFR
)
Hall-Effect Sensor Input Terminal Flag Bit (HPF)
This read/write flag is set depending on RUN/STOP
mode.
RUN Mode
An interrupt will be generated when a state change on any
enabled Hall-effect sensor input terminal is detected. Clear
HPF by writing a Logic [1] to HPF. Reset clears the HPF bit.
Writing a Logic [0] to HPF has no effect.
1 = State change on the hallflags detected
0 = No state change on the hallflags detected
STOP Mode
An interrupt will be generated when AWDCC is set and a
current above the threshold is detected on any enabled Hall-
effect sensor input terminal. Clear HPF by writing a Logic [1]
to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF
has no effect.
1 = One or more of the selected Hall-effect sensor input
terminals had been pulled HIGH
0 = None of the selected Hall-effect sensor input
terminals has been pulled HIGH
LIN Flag Bit (LINF)
This read/write flag is set on the falling edge at the LIN
data line. Clear LINF by writing a Logic [1] to LINF. Reset
clears the LINF bit. Writing a Logic [0] to LINF has no effect.
1 = Falling edge on LIN data line has occurred
0 = Falling edge on LIN data line has not occurred since
last clear
High-Temperature Flag Bit (HTF)
This read/write flag is set on
a
high-temperature condition.
Clear HTF by writing a Logic [1] to HTF. If a high-temperature
condition is still present while writing a Logic [1] to HTF, the
writing has no effect. Therefore, a high-temperature interrupt
cannot be lost due to inadvertent clearing of HTF. Reset
clears the HTF bit. Writing a Logic [0] to HTF has no effect.
1 = High-temperature condition has occurred
0 = High-temperature condition has not occurred
Low-Voltage Flag Bit (LVF)
This read/write flag is set on a low-voltage condition. Clear
LVF by writing a Logic [1] to LVF. If a low-voltage condition is
still present while writing a Logic [1] to LVF, the writing has no
effect. Therefore, a low-voltage interrupt cannot be lost due
to inadvertent clearing of LVF. Reset clears the LVF bit.
Writing a Logic [0] to LVF has no effect.
1 = Low-voltage condition has occurred
0 = Low-voltage condition has not occurred
High-Voltage Flag Bit (HVF)
This read/write flag is set on a high-voltage condition.
Clear HVF by writing a Logic [1] to HVF. If high-voltage
condition is still present while writing a Logic [1] to HVF, the
writing has no effect. Therefore, a high-voltage interrupt
cannot be lost due to inadvertent clearing of HVF. Reset
clears the HVF bit. Writing a Logic [0] to HVF has no effect.
1 = High-voltage condition has occurred
0 = High-voltage condition has not occurred
Overcurrent Flag Bit (OCF)
This read-only flag is set on an
overcurrent condition.
Reset clears the OCF bit. To clear this flag, write a Logic [1]
to the appropriate overcurrent flag in the SYSSTAT Register.
See
Figure 10
,illustrating the three signals triggering the
OCF.
1 = High-current condition has occurred
0 = High-current condition has not occurred
Figure 10. Principal Implementation for OCF
Register Name and Address: IFR - $05
Bits
7
6
5
4
3
2
1
0
Read
0
HPF
LINF
HTF
LVF
HVF
OCF
0
Write
Reset
0
0
0
0
0
0
0
0
OCF
HVDD_OCF
HS_OCF
HB_OCF