參數資料
型號： 84C24
廠商： LSI Corporation
英文描述： Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網媒體接口適配器)
中文描述： 四10Base - T以太網媒體接口適配器（四通道10Base - T的以太網媒體接口適配器）
文件頁數： 9/51頁
文件大?。?/td> 435K
代理商： 84C24
84C24
4-9
9
MD400147/A
3.7.3 Receive Level Adjust
The receiver squelch and unsquelch evels can be owered
by 4.5 dB by setting the receive evel adjust bit n the serial
port Channel Configuration register. By setting this bit, the
device can support cable lengths exceeding 100 meters.
3.8 SOI (Start of Idle)
The SOI pulse is a positive pulse inserted at the end of
every transmitted packet on the twisted pair wire to
indicate the end of transmission and the start of idle.
The TP transmitter generates an SOI pulse at the end of
data transmission when TXEN is deasserted. The TP
transmitted SOI output pulse is shaped by the transmit
waveshaper to meet the pulse template requirements
specified n IEEE 802.3 Section 14 and shown n Figure 4.
The TP receiver detects the SOI pulse by sensing missing
data transitions. Once the SOI pulse is detected, data
reception is ended and CSN is deasserted.
3.9 LINK INTEGRITY & AUTONEGOTIATION
3.9.1 General
The 84C24 can be configured to implement either the
IEEE 802.3 Clause 14 10Base-T link algorithm for link
integrity or the IEEE 802.3 Clause 28 Link Signaling
algorithm for both ink ntegrity and AutoNegotiation of Full
or Half Duplex operation with a remote device. The choice
of either standard 10Base-T ink algorithm or AutoNegotia-
tion link algorithm is made by setting the AutoNegotiation
enable bit in serial port Global Configuration register. Per
the IEEE specification, the 84C24 can interoperate with a
remote device that does not implement the IEEE 802.3
Clause 28 AutoNegotiation algorithm as long as the re-
mote device has the 10Base-T link integrity algorithm.
3.9.2 10Base-T Link Integrity Algorithm
The transmit and receive 10Base-T algorithms are the
same as defined in IEEE 802.3 Clause 14. The 10Base-
T algorithm uses normal link pulses, or NPL’s to establish
link integrity. The transmit link pulse meets the template
defined in IEEE 802.3 Clause 14 and shown in Figure 5.
Refer o he EEE 802.3 Clause 14 section on Link ntegrity
for more details.
3.9.3 AutoNegotiation Algorithm
The transmit and receive AutoNegotiation algorithms are
the same as defined in IEEE 802.3 Clause 28. The
AutoNegotiation algorithm uses a burst of link pulses,
called fast link pulses (FLP), to pass up to 16 bits of
signaling data back and forth between the 84C24 and a
remote device. The transmit FLP’s meet the template
defined n IEEE 802.3 Clause 14 and shown n Figure 5. A
timing diagram contrasting NLP’s and FLP’s is shown in
Figure 6. Each of the four channels on the 84C24 has an
independent and separate AutoNegotiation state ma-
chine.
In the 84C24 the FLP’s are used to advertise either Full or
Half Duplex capability to a remote device. The 84C24 Full
and Half Duplex advertisement capabilities are pro-
grammed by setting the duplex select bits n the serial port
Channel Configuration registers.
The AutoNegotiation algorithm s nitiated when any of the
following events occurs: (1) Powerup, (2) device reset, (3)
AutoNegotiation reset, (4) device enters Link Fail State, or
(5) AutoNegotiation enable bit s set. Once he negotiation
process s completed, he 84C24 configures tself or either
Full or Half Duplex Operation, depending on the outcome
of the AutoNegotiation. The result of the AutoNegotiation
process for each channel s stored n the duplex detect bits
in the serial port Channel Status Registers. When the
AutoNegotiation process is completed, the 84C24
switches back to the 10Base-T ink ntegrity algorithm with
NLP’s.
The status of the negotiation process for each channel can
be viewed by reading he AutoNegotiation status bits n he
serial port Channel Status registers.
The AutoNegotiation algorithm embedded inside the
84C24 is more complicated than stated above. If more
details are needed, refer to IEEE 802.3 Clause 28.
3.9.4 Link Indication
The receive link detect status is available as a bit in serial
port Channel Status register and it can also be pro-
grammed to appear on the PLED[3:0] pins if the program-
mable LED output select bits are set appropriately in the
Global Configuration register. When PLED[3:0] pins are
programmed as link pulse detect outputs, they are indi-
vidually asserted ow when that channel s n the Link Pass
State. The PLED[3:0] outputs are open drain with resistor
pullups and can drive and LED from V
CC
or can drive
another digital input.
3.9.5 Link Disable
The ink pulse unction can be disabled or each channel by
setting the link disable bit in the serial port Channel
Configuration registers. When the link pulse function is
disabled for that channel, the device gnores the reception
of link pulses, stays in the Link Pass State, continues to
transmit NLP’s and configures itself for Full or Half Duplex
based on he value of he duplex select bits n he serial port
Channel Configuration registers.
相關PDF資料
PDF描述
84C300A 84C300A 4-Port Fast Ethernet Controller manual 3/98
84C30A 84C30A 10 Mbps Controller (MAC) manual 12/96
84C300A 4-Port Fast Ethernet Controller(四端口快速以太網控制器)
84CNQ035 Schottky Rectifier
84CNQ040 Schottky Rectifier
相關代理商/技術參數
參數描述
84C2A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-K06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*