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參數(shù)資料
| 型號： | 84C24 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器) |
| 中文描述： | 四10Base - T以太網(wǎng)媒體接口適配器（四通道10Base - T的以太網(wǎng)媒體接口適配器） |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 435K |
| 代理商： | 84C24 |
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84C24
4-25
MD400147/A
Keep he external resistor close o he REXT and GND pins
as possible in order to reduce noise pickup into the
transmitter.
Since the TPO
±
output is a current source, capacitive and
inductive loading can reduce the output voltage level from
the ideal. Thus, in actual application, it might be neces-
sary to adjust the value of the output current to compen-
sate for external loading. One way to adjust the TPO
±
output level is to change the value of the external resistor
tied to REXT as discussed in the previous paragraphs. A
better way to adjust the TPO
±
output level is to use the
transmit level adjust register bits accessed through the
serial port. These four bits can adjust the output level by
-18% to +24% in 6% steps as described in Table 1.
5.5 CONTROLLER INTERFACE
The controller interface will connect to any of the following
Ethernet controllers, without any glue logic, as shown in
Figure 7 and 8.
Standard Ethernet controllers use TXC to clock data on
TXD. TXC s specified on standard Ethernet controllers to
be an output. If a nonstandard controller is used, there
might be a need to clock TXD nto the 84C24 on the edges
of an external master clock. The master clock, n his case,
would be an nput to the 84C24. This can be done by using
OSCIN as the master clock input. OSCIN generates TXC
inside the 84C24; thus, TXD data can be clocked into the
84C24 on edges of output clock TXC or nput clock OSCIN.
In the case where OSCIN is used as the input clock, a
crystal s no onger needed on OSCIN, and TXC can be eft
open or used for some other purpose.
5.6 SERIAL PORT
5.6.1 General
The 84C24 has a serial port to set all of the device’s
configuration nputs and read out the status outputs. Most
microcontrollers can easily interface to the serial port
without any extra logic, as shown in Figure 7 and 8.
As described earlier, the serial port consists of 8 lines:
SCLK, SDIO, INT, CS, and SA[3:0]. However, only three
lines, SCLK, SDIO, and CS are needed to shift data n and
out. INT is provided for convenience only and SA[3:0] are
usually pinstrapped to the correct device address.
The CS signal can be extended such hat multiple registers
can be read out in a single serial port read cycle.
5.6.2 Polling vs. Interrupt
The status output status bits can be monitored by either
polling the serial port or with interrupt.
If polling is used, the registers can be read by an external
device at regular intervals and the status bits can be
checked against their previous values to determine any
changes. To make polling simpler, multiple registers can
be accessed on a single read cycle by extending CS. This
eliminated the need to poll registers individually.
The interrupt feature offers the ability to detect changes in
the status output bits without constant register polling.
Assertion of the INT pin or INT and INT_GLBL serial port
bits ndicates that one or more of the status output bits has
changed since the last read cycle. Thus, any of these
interrupt signals can be used by an external device to
initiate a read cycle. Then the individual registers (or
multiple registers) can be read out and status bits com-
pared against their previous values to determine any
changes. If the register address REGAD[3:0] = 1111 is
selected, the serial port will automatically go to the register
that has the ”interrupted bit“, thus eliminating the need to
read all four Channel Status registers in response to a
single interrupt. If multiple bits asserted the interrupt and
REGAD[3:0] = 1111 is used to access them, the inter-
rupted registers are accessed in numerical order on each
read cycle. After all the interrupt bits have been read out,
the nterrupt signals are deasserted. A mask register bit or
every status output bit exists n he Global Mask register so
that the interrupt bits can be individually programmed for
each application.
5.6.3 Serial Port Addressing
The device address for the serial port is selected by tying
the SA[3:0] pins to the desired value. SA[3:0] share the
same pins as the PLED[3:0] outputs, respectively, as
shown n Figure 9a. At powerup or reset, he output drivers
are tristated for an interval called the power-on reset time.
During the power-on reset nterval, the value on these pins
is latched into the device and used as the serial port
address. The LED outputs are open drain with internal
resistor pullup to V
CC
.
If an LED is desired on the LED outputs, then an LED and
resistor are tied to V
as shown in Figures 9b. If a high
address is desired, then the LED to V
automatically
makes the latched address value a high. If a low value for
the address s desired, then a 50K resistor to GND must be
added as shown in Figure 9b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C300A | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C2A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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