參數(shù)資料
型號(hào)： 84C24
廠商： LSI Corporation
英文描述： Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器)
中文描述： 四10Base - T以太網(wǎng)媒體接口適配器（四通道10Base - T的以太網(wǎng)媒體接口適配器）
文件頁(yè)數(shù)： 6/51頁(yè)
文件大?。?/td> 435K
代理商： 84C24
84C24
4-6
MD400147/A
3.0 Functional Description
3.1 INTRODUCTION
The 84C24 is a highly integrated analog interface IC's for
twisted pair Ethernet applications (10Base-T).
The 84C24 consists of four (4) separate and independent
channels, each consisting of: Manchester encoder,
twisted pair transmitter with wave shaping and on chip
filters, twisted pair transmit output driver, twisted pair
receiver with on chip filters, Manchester decoder, and
controller nterface. The 84C24 also has a serial port o set
configuration inputs and read status outputs for each
channel.
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters and
common mode chokes normally required in 10Base-T
applications.
The 84C24 is ideal as a media interface for 10Base-T
switching hubs, routers, bridges, servers, and other mul-
tiport devices.
3.2 GENERAL
The 84C24 has four independent 10Base-T Media Inter-
face Adapter channels. Each channel has six main
sections: controller interface, Manchester encoder, Man-
chester decoder, twisted pair transmitter, twisted pair
receiver, and collision sense. There is also a serial port
and a crystal oscillator that s common to all four channels.
On he ransmit side, NRZ data s received on he controller
interface from an external controller. The data s then sent
to the Manchester encoder for formatting. The Manch-
ester encoded data s then sent to the TP transmitter. The
TP transmitter is composed of a waveform generator that
preshapes the output, a filter to remove high frequency
components, and an output driver to drive the 100 ohm
twisted pair cable. In addition, the transmitter generates
link pulses, start of idle (SOI) pulses, and detects the
jabber condition.
On the receive side, the twisted pair receiver receives
incoming Manchester encoded data from the twisted pair
cable, removes high frequency noise from the input,
determines if the input signal is a valid packet, and then
converts the data from twisted pair evels to nternal digital
levels. The twisted pair receiver also detects link pulses,
detects start of idle (SOI) pulses, detects and corrects for
reverse polarity on the twisted pair inputs, implements a
squelch algorithm o reject nvalid signals, and detects and
enables Full Duplex operation. The output of the twisted
pair receiver then goes to the Manchester encoder which
recovers a clock from the TP data stream, recovers the
data, and converts the data back to NRZ. The NRZ data
is then transmitted to an external controller through the
controller interface.
The crystal oscillator generates a master clock for the
device. The serial port s a bidirectional port through which
configuration inputs can be set and status outputs can be
read out.
Each block plus the operating modes are described in
more detail in the following sections. A block diagram of
the 84C24 is shown in Figure 1.
3.3 CONTROLLER INTERFACE
The 84C24 can directly connect, without any external
logic, to Ethernet controllers manufactured by SEEQ,
Intel, NSC, and AMD. The selection of controller nterface
type s done by setting the controller nterface select bits n
the serial port Global Configuration register.
The controller interface signal pins are transmit data
(TXD), transmit clock (TXC), transmit enable (TXEN),
receive data (RXD), receive clock (RXC), carrier sense
(CSN), collision (COL).
On the transmit side, when TXEN is deasserted, no data
is transmitted. When TXEN is asserted, data on TXD is
clocked into the device on the edges of the TXC output
clock. Since OSCIN nput clock generates the TXC output
clock, TXD data is also clocked in on edges of OSCIN.
On the receive side, when nvalid data s sensed on the TP
inputs, the receiver s dle. During dle, CSN s deasserted,
RXD is held either low (SEEQ, NSC) or high (Intel, AMD),
and RXC either follows TXC (Seeq) or is held low (Intel,
AMD, NSC). When a valid packet is detected on the TP
receive inputs, CSN is asserted and the clock recovery
process starts on the incoming data. After the receive
clock has been recovered from the data, RXC is either
switched from TXC to the recovered data clock (SEEQ
mode) or RXC is switched from low to the recovered data
clock (Intel, AMD, NSC). The recovered NRZ data is
clocked out on RXD on edges of the RXC clock. When the
end of packet is detected on the TP input, CSN is
deasserted. After CSN deassertion, RXC is either
switched over to TXC (SEEQ) or held low (Intel, AMD,
NSC).
The collision output, COL, is asserted whenever the colli-
sion condition is detected.
相關(guān)PDF資料
PDF描述
84C300A 84C300A 4-Port Fast Ethernet Controller manual 3/98
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84C300A 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
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84C2A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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