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參數(shù)資料
| 型號： | 84C24 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器) |
| 中文描述： | 四10Base - T以太網(wǎng)媒體接口適配器（四通道10Base - T的以太網(wǎng)媒體接口適配器） |
| 文件頁數(shù)： | 7/51頁 |
| 文件大小： | 435K |
| 代理商： | 84C24 |
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84C24
4-7
7
MD400147/A
The output pin PLED can be configured to be a Full Duplex
output by appropriately setting the programmable LED
output select bits in the serial port Global Configuration
register. A Full Duplex Detect status bit s also available n
the serial port Channel Status register.
3.4 MANCHESTER ENCODER
Manchester encoding is the process of combining the
clock and data together into one serial stream to be
transmitted onto the twisted pair wire. To Manchester
encode data, the first half of the data bit contains the
complement of the data, and the second half of the data bit
contains the true data. This guarantees that a transition
always occurs in the middle of the bit cell. Manchester
encoding of the data from TXD occurs only when TXEN s
asserted.
3.5 MANCHESTER DECODER
Manchester decoding is the process of extracting clock
and data from a Manchester encoded data stream. In
Manchester encoded data, the first half of the data bit
contains the complement of the data, and the second half
of the data bit contains the true data.
Clock recovery is done with a PLL. When valid data is not
detected on the receive input, the 10 MHz TXC clock is
applied o he nput of he PLL. When valid data s detected
on the TP receive input, the PLL input is switched to the
incoming data. The PLL hen recovers he clock by ocking
onto zero crossings of the ncoming signal from the twisted
pair wire. The recovered RXC clock frequency s 10 MHz.
The PLL can ock onto the preamble signal n ess than 12
transitions (bit times) and can reliably perform the data
recovery process with up to
±
13.5 nS of jitter on the TP
input. While the PLL is in the process of locking onto the
preamble signal, some of the preamble data symbols are
lost. The clock recovery process recovers enough pre-
amble data symbols to pass at least 5 bytes of preamble
to the receive controller interface.
Data recovery s done by atching n data from the receiver
with the recovered clock extracted by the PLL.
3.6 TWISTED PAIR TRANSMITTER
3.6.1 Transmitter
The transmitter consists of a waveform generator and ine
driver.
The purpose of the waveform generator is to shape the
output ransmit pulse. The waveform generator consists of
a ROM, DAC, clock generator, and filter. The DAC
generates a stair-stepped representation of the desired
output waveform. The stairstepped DAC output hen goes
through a low pass filter in order to "smooth" the DAC
output and remove any high frequency components. The
DAC values are determined from the ROM outputs; the
ROM outputs are chosen to shape the pulse to the desired
template and are clocked nto he DAC at high speed by he
clock generator. In this way, the waveform generator
preshapes the output waveform transmitted onto the
twisted pair cable o meet he pulse emplate requirements
outlined in IEEE 802.3 Section 14 and also shown in
Figure 2. The waveshaper replaces and eliminates exter-
nal filters on the TP transmit output.
The line driver converts the preshaped and smoothed
waveform to a current output that can drive 0-100 meters
of 100 ohm UTP or 150 ohm STP twisted pair cable tied
directly to pins TPO
±
without any external filters. During
the idle period, no output signal is transmitted on TPO
±
(except link pulse).
3.6.2 Transmit Level Adjust
The ransmit evel can be adjusted with hree ransmit evel
adjust bits in the serial port Global Configuration register
as shown in Table 1. The adjustment range is -18% to
+24% in 6% steps.
The 84C24 has special circuitry to reduce common mode
noise on the twisted pair output. Common mode chokes
may not be needed to meet emissions requirements in
most applications.
3.6.3 Transmit Disable
The TP transmitter can be disable by setting the transmit
disable bit n he serial port Channel Configuration register.
When disabled, the TP transmitter is forced into the idle
state with link pulses not transmitted, even if TXEN is
asserted.
Table 1. Transmit Level Adjust
TLVL3-1
000
001
010
011
100
101
110
111
Gain
1.24
1.18
1.12
1.06
1.00
0.94
0.88
0.82
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C300A | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C2A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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