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參數(shù)資料
| 型號(hào)： | 84C24 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器) |
| 中文描述： | 四10Base - T以太網(wǎng)媒體接口適配器（四通道10Base - T的以太網(wǎng)媒體接口適配器） |
| 文件頁數(shù)： | 12/51頁 |
| 文件大?。?/td> | 435K |
| 代理商： | 84C24 |
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84C24
4-12
MD400147/A
3.10 COLLISION
Collision occurs whenever transmit and receive occur
simultaneously on TPO
±
outputs and TPI
±
nputs. COL s
asserted when collision occurs. COL is also asserted
when the jabber condition has been detected and when
the SQE test is performed. Collision function is disabled if
the device is in the Link Fail State or Full Duplex mode.
3.11 SIGNAL QUALITY ERROR (SQE)
The controller nterface connection s continually tested by
transmitting a 1
μ
s collision pulse on the collision output,
COL, after each transmit packet. This is known as the
signal quality error (SQE) test.
The SQE test s disabled when the device s n the Link Fail
state or when jabber is detected. SQE test can also be
enabled by setting the SQE enable bit in the serial port
Global Configuration register. See the Serial port section
for more details.
3.12 JABBER
Jabber condition occurs when the transmit packet ex-
ceeds its maximum allowable length. When jabber is
detected, the transmit outputs on TPO
±
are forced to the
idle state, collision is asserted, and the jabber detect bit
is set n the serial port Channel Status register. In addition,
jabber function can be disabled by setting a abber disable
bit in the serial port Global Configuration register.
3.13 RECEIVE POLARITY CORRECTION
The polarity of the signal on the receive input twisted pair
pins , TPI
±
, s continuously monitored. If either 3 consecu-
tive SOI or 3 consecutive link pulses indicate incorrect
polarity on TPI
±
, the polarity s nternally determined to be
incorrect. If reverse polarity is detected, the reverse
polarity detect bit is set in the serial port Channel Status
register.
The 84C24 will automatically correct for the reverse polar-
ity condition with the autopolarity eature. Autopolarity can
be disabled by setting the autopolarity disable bit in the
serial port Global Configuration register.
3.14 FULL DUPLEX MODE
Full Duplex mode allows transmission and reception to
occur simultaneously. When Full Duplex mode is en-
abled, collision is disabled, internal loopback is disabled,
and SQE pulse is disabled.
The device can be orced nto he Half or Full Duplex mode,
or the device also can detect either Half or Full Duplex
capability from a remote device and automatically place
itself in the correct mode.
The device can be forced into the Full or Half Duplex
modes by setting the duplex bits in the serial port Channel
Configuration register.
The device can automatically configure itself for Full or
Half Duplex modes by using the AutoNegotiation scheme
to advertise and detect Full and Half Duplex capabilities to
and from a remote terminal. All of this is described in
gruesome detail in the Link Integrity And AutoNegotiation
section. AutoNegotiation can be enabled by setting the
AutoNegotiation enable bit in the serial port Global Con-
figuration register.
Full Duplex detect status output bit s available n the serial
port Channel Status register and it can also be pro-
grammed to appear on the PLED[3:0] pin by setting the
programmable LED output select bits in the serial port
Global Configuration register. When PLED[3:0] is pro-
grammed as Full Duplex detect output, it is asserted low
when the device is in the Full Duplex mode, either forced
or autodetected. The PLED[3:0] output s open drain with
resistor pullup and can drive an LED from V
CC
or can drive
another digital input.
3.15 LOOPBACK
In order to emulate coax Ethernet behavior, transmitted
data on TPO
±
is normally internally looped back onto the
receive section and sent out on the receive controller pins
RXD, CSN, and RXC as f t was a regular received packet.
The oopback unction s disabled f he device s n he Link
Fail State, jabber condition, or in Full Duplex mode.
Diagnostic loopback can be implemented by disabling the
transmitter and sending a ransmit packet. The ransmitter
can be disabled by setting the transmit disable bit in the
serial port Channel Configuration register.
3.16 RESET
The 84C24 can be reset by setting the reset bit n the serial
port Global Configuration register, by asserting the
RESET pin active low, or by applying V
CC
to the device.
When the reset bit is set, an internal powerup reset pulse
is generated which resets all internal timers and state
machines and forces the serial port bits to their default
values. After the powerup reset pulse has finished, the
reset bit in the serial port Global Configuration register is
cleared.
When the reset pin RESET s forced ow, all nternal timers
and state machines are reset and the serial port bits are
forced to their default values. After the RESET pin is let
go or forced high, the device returns to normal operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84C300A | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
| 84CNQ040 | Schottky Rectifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C2A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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