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參數(shù)資料
| 型號(hào)： | 80C03 |
| 廠商： | LSI Corporation |
| 英文描述： | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 中文描述： | AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制（AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器） |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
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80C03
4-7
MD400121/C
The OLD/NEW status bit is set each time the Transmit
Status Register is read, and reset each time new status is
loaded into the Transmit Status Register. The OLD/NEW
status bit is SET, and all other bits CLEARED upon chip
reset.
Transmit Status Register Format
the received destination address. The Station Address
should be programmed prior to enabling the receiver.
Transmit Command Register
The Transmit Command Register is an interrupt mask
register, which provides for control of the conditions al-
lowed to generate transmit interrupts. Each of the four
least significant bits of the register may be individually set
or cleared. When set, the occurrence of the associated
condition will cause an nterrupt to be generated. The four
specific conditions for which interrupts may be generated
are:
Underflow
Collision
16 Collisions
Transmission Successful
The nterrupt signal INT will be set when one or more of the
specified transmission termination conditions occurs and
the associated command bit has been set. The interrupt
signal INT will be cleared when the Transmit Status
Register is read.
All bits of the Transmit Command Register are cleared
upon chip reset.
Transmit Command Register Format
Transmission Successful is set only on the successful
transmission or retransmission of a frame.
80C03 provides additional new features which are en-
abled depending on writing ‘1’s to bits 7,6,5,4 of the
transmit command register. If hese our bits are always 0’
then the 80C03 will be exactly compatible to SEEQ 8003
EDLC.
The bits 6,5 of transmit command register are used to
address new registers on 80C03 together with the A2, A1,
A0, RD WR, CS pins. (see table Page 9)
Transmit Status Register
The Transmit Status Register is loaded at the conclusion
of each frame transmission or retransmission attempt. It
provides for the reporting of both the normal and error
termination conditions of each transmission.
Receive Command Register
The Receive Command Register has two primary func-
tions, t specifies the Address Match Mode, and t specifies
Frames-of Interest. i.e. frames whose arrival must be
communicated to the CPU via interrupts and status regis-
ter updates. Frames-of-Interest are frames whose status
must be saved or nspection, even at he expense of osing
subsequent frames.
Receive Command Register Format
Bits 0-5 specify Interrupt and Frame-of-Interest when set.
Bit 4, End of Frame, specifies any type of frame except
overflow.
Interrupt on Overflow Error
Interrupt on CRC Error
Interrupt on Dribble Error
Interrupt on Short Frame
Interrupt on End of Frame
Interrupt on Good Frames
Match Mode 0
Match Mode 1
7
6
5
3
2 1
4
0
BIT
Transmit Underflow
Transmit Collision
16 Transmission Attempts
Transmission Successful
7
6
5
3
2 1
4
x
x
x
0
BIT
Old/New Status
Interrupt on Transmit Underflow
Interrupt on Transmit Collision
Interrupt on 16 Transmission
Attempts
Interrupt on Transmission
Successful
7
6
5
3
2 1
4
0
0
0
0
0
BIT
If ‘1’ Enable
Additional Features
If ‘0’ 8003 Mode
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