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參數(shù)資料
| 型號(hào)： | 80C03 |
| 廠商： | LSI Corporation |
| 英文描述： | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 中文描述： | AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制（AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器） |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
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80C03
4-11
MD400121/C
Transmit Packet Autopad Mode
This feature automatically pads packets to be transmitted
with less than 60 bytes of data out to a minimum IEEE
802.3 standard packet length of 60 bytes excluding FCS.
Padding is done with bytes of 00 hex.
Transmit No Preamble Mode
This mode prevents the transmitter from adding a pre-
amble pattern at the beginning of data to be transmitted.
Receive Own Transmit Disable Mode
This mode prevents the 80C03 from receiving a packet if
it is also transmitting a packet.
Transmit No CRC Mode
This mode prevents the transmitter from appending trans-
mit data with an FCS.
AutoDUPLEX Mode
In this mode the transmitter will ignore carrier sense and
will not defer to it if it is ready to transmit a packet.
Receive CRC Mode
In this mode the receiver loads the 4 bytes of FCS into the
receive FIFO along with the data allowing the FCS value
to be read out.
Fast Receive Discard Mode
In this mode the receive discard signal RxDC occurs a
maximum of 400 ns after carrier sense goes low.
Pin Description
The EDLC chip has four groups of interface signals:
Power Supply
Encoder/Decoder
Data Buffer
Command/Status
Power Supply
V
CC
..........................................................................+5V
V
SS
.....................................................................Ground
Encoder/Decoder Interface
TxC
Transmit Clock (Input):
10 MHz, 50% duty cycle
transmit clock used to synchronize the transmit data from
the EDLC chip to the encoder. This clock runs continu-
ously, and is asynchronous to RxC.
TxD Transmit Data (Output):
Serial Data output to the
encoder. Active HIGH.
TxEN Transmit Enable (Output):
This signal is used to
activate the encoder. It becomes active when the first bit
of the Preamble is transmitted and inactive when the last
bit of the frame s transmitted. Active HIGH and cleared by
Reset.
RxC Receive Data (Input):
10 MHz, 50% duty cycle
nominal. The receive clock is used to synchronize incom-
ing data to the EDLC chip from the decoder. This clock
runs continuously, and is asynchronous to TxC.
RxD Receive Data (Input):
Serial input data to the EDLC
chip from the decoder. Active HIGH.
CSN Carrier Sense (Input):
Indicates traffic on the coax-
ial cable to the EDLC chip. Becomes active with the first
bit of the Preamble received, and nactive one bit time after
the last bit of the frame is received. Active HIGH.
COLL Collision (Input):
Indicates transmission conten-
tion of the Ethernet cable. the Collision input is latched
internally. Sampled during ransmission, Collision s set by
an active high pulse on the COLL input and automatically
reset at the end of transmission of the JAM sequence.
Data Buffer Interface
RxTxD (0-7) Receive/Transmit Data Bus (I/O):
Carries
Receive/Transmit data byte from/to the EDLC chip Re-
ceive/Transmit FIFOs.
RxTxEOF Receive/Transmit End of Frame (I/O):
Indi-
cates last byte of data on the Receive/Transmit Data Bus.
Effectively a ninth bit in the FIFOs with identical timing to
RxTxD (0-7). Active HIGH.
RxRDY Receive Ready (Output):
Indicates that at least
one byte of received data s available n the Receive FIFO.
This signal will remain active high as long as one byte of
data remains n the Receive FIFO. When this condition no
longer exists, RxRDY will be deasserted with respect to
the eading edge of the RxRD strobe that removes the ast
byte of data from the Receive FIFO. RxRD should not be
activated if RxRDY is low. Active HIGH and cleared by
Reset.
RxRD Receive Read Strobe (Input):
Enables transfer of
received data from the EDLC Receive FIFO to the RxTxD
Bus. Data is valid from the EDLC Receive FIFO at the
RxTxD pins on the rising edge of this signal. This signal
should not be activated unless RxRdy s high. Active LOW.
RxDC Receive Discard (Output):
Asserted when one of
the following conditions occurs, and the associated Inter-
rupt Enable bit n the Receive Command Register s reset.
(1) Receive FIFO overflow. (2) CRC Error. (3) Short Frame
Error. (4) Receive frame address nonmatch or (5) current
frame status lost because previous status was not read.
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