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參數(shù)資料
| 型號(hào)： | 80C03 |
| 廠商： | LSI Corporation |
| 英文描述： | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 中文描述： | AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制（AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器） |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
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80C03
4-5
MD400121/C
TRANSMIT
RECEIVE
DATA
BUFFER
BUS
TRANSCEIVER
DMA/
BUFFER
CONTROL
CPU
SYSTEM
MEMORY
80C03
EDLC
8020 or 8023
MANCHESTER
CODE
CONVERTER (MCC)
COLLISION
TRANSMIT
RECEIVE
TO 83C92 CMOS COAX TRANSCEIVER
83C94 CMOS TWISTED PAIR TRANSCEIVER
Figure 5. Typical Ethernet Node Configuration
Address Matching
Ethernet addresses consist of two 6-byte fields. The first
bit of the address signifies whether it is a Station Address
or a Multicast/Broadcast Address.
mine which byte is selected and bits 3 thru 5 to determine
which bit according to the following tables:
FCS Bits
0
1
Byte Selected
2
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
Byte 0
Byte 1
Byte 2
Byte 3
Byte 7
FCS Bits
4
5
Bit Selected
6
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 7
Multicast Address:
If the first bit of the incoming address
is a 1 and the EDLC chip is programmed to accept
Multicast Addresses without using Hash filtering, the
frame s received. The 80C03 also can be programmed to
use hash filter for determining acceptance of multicast
addresses.
First Bit
0
Address
Station Address (Physical)
1
Multicast/Broadcast Address
(logical)
Address matching occurs as follows:
Station Address:
All destination address bytes must
match the corresponding bytes found in the Station Ad-
dress Register. If Group Address mode s enabled, he ast
4 bits of he station address are masked out during address
matching.
After computing the FCS on the first six bytes of the
address field (Destination address), the 80C03 uses bits 0
thru 5 as an address to the Multi-cast address filter
register. Bit 0 of the FCS is assumed to be where receive
data enters the FCS generation circuitry. If the corre-
sponding bit addressed in the Multicast address filter
register s a 1’ the 80C03 will receive the frame, otherwise
it will discard the frame. Addressing of the Multicast
address filter register occurs using bits 0 thru 2 to deter-
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