參數(shù)資料
型號(hào): 80C03
廠商: LSI Corporation
英文描述: AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器)
中文描述: AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制(AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器)
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 247K
代理商: 80C03
80C03
4-14
MD400121/C
Limits
Typ.
Units
(ns)
Symbol
[5]
DATA AND COMMAND/STATUS INTERFACE TIMING
TDBD
RxTx/CdSt Bus Data Delay
TDBR
RxTx/CdSt Bus Release Delay
TDBS
RxTx/CdSt Bus Siezure Delay
TDRY
RxRDY/TxRDY Clear Delay
THAR
A
0-2
/CS Hold
THDA
RxTx/CdSt Bus Hold
THRW
RxRD/TxWR Hold
TSAR
A
0-2
/CS Setup
TSCS
CdSt Bus Setup
TSRT
RxTx Bus Setup
TWCH
RxRD/TxWR/RD/WR High Width
TWCL
RxRD/TWR/RD/WR Low Width
Parameter
Min.
Max.
Condition
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
20
40
10
0
0
0
20
20
50
50
10,000
AC Test Conditions
Output Load: 1 Schottky TTL Gate + CL = 100 pF
(All pins except TxEN, TxD)
TxEN, TxD Load: 1 Schottky TTL Gate + CL = 35 pF
Input Pulse Level:0.4 V to 2.4 V
Timing Reference Level:1.5 V
AC Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
5%
Capacitance
[6]
T
A
= 25
°
C, F
C
= 1 MHz
Symbol Parameter
Maximum
Condition
C
IN
Input Capacitance
15 pF
V
IN
= 0 V
C
I/O
I/O Capacitance
15 pF
V
I/O
= 0 V
SERIAL TRANSMIT AND RECEIVE INTEFACE TIMING
TDDC
RxDC Set Delay
TDIC
INT Clear Delay
TDRE
TxRET Set Delay
TDRI
Receive INT Delay
TDTD
TxD/TxEN Delay
TDTI
Transmit INT Delay
THRD
RxD Hold
TPCK
RxC/TxC Clock Period
TSRD
RxD Setup
TWDC
RxDC High Width
TWRC
RxC High/Low Width
TWRE
TxRET High Width
TWRS
RESET Low Width
950
1650
45
3400
1850
60
3600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE 1
2400
1150
20
2600
20
95
30
800
45
800
10,000
NOTE 3
NOTE 2
CI = 35 pF
NOTE 4
1000
TWTC
TWCO
TxC High/Low Width
COLL Width
45
200
ns
ns
NOTES:
1. For frame reception with Shortframe or CRC Error. If frame reception is terminated due to Overflow, RxDC will be issued within 1.2
μ
s of Overflow. If frame
reception is terminated due to non-match of address, RxDC wil be issued within 2.4
μ
s of the receipt of the last address bit. If Fast Receive Discard Mode
is enabled, the maximum delay of RXDC is 400 ns.
2. Normal frame reception without Overflow. If frame reception is terminated due to Overflow, INT will be issued within 1.2
μ
of Overflow.
3. For TxRET caused by Collision or 16 Collision condition. If transmission is terminated due to UnderflowTxRET will be issued within 1.2
μ
s of the Underflow.
4. For INT caused by Collision or 16 Collision condition. If caused by Underflow, INT will be issued within 1.1
μ
s. If caused by normal termination, INT will
be issued within 200 ns of TxEN going LOW.
5. Italics indicate input requirement, non-italics indicate output timing.
6 Characterized. Not tested.
相關(guān)PDF資料
PDF描述
80C154S Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-DFN, T/R
83C154S CMOS 8-bit Microcontroller(258.00 k)
81400000 LACING CORD 25M RL
81451 BECHERKLEMME T2123
2124 REAKTIONSGEFAESSKLEMME T2124
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80C07B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES
80C08C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES
80C151SB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE CHMOS MICROCONTROLLER
80C152 制造商:Intel 功能描述:
80C152JA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER